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PDF INDT165B Data sheet ( Hoja de datos )

Número de pieza INDT165B
Descripción (INDx165B / INDx330B) Long Distance Digital Display Link Transmitter & Receiver
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Data Sheet
INDT/R165B
INDT/R330B
Order this document by Q_DS_GigaSTaR_DDL
Long Distance Digital Display
Link Transmitter & Receiver
The GigaSTaRDigital Display Link is an innovative
high-speed interconnect featuring simultaneous trans-
mission of digital video, audio and bi-directional side-
band data over a standard shielded twisted pair cable up
to 50 m (500 m with fiber optics). It supports VESA video
resolution standards ranging from VGA to XGA
(INDT/R165B) or to UXGA (INDT/R330B) with up to 16.7
million colors. The sideband channels provide bandwidth
up to 264 Mbps to connect peripheral components like
keyboard, mouse, disc drive and audio devices.
Features:
Supported VESA video resolutions:
INDT/R165B: VGA XGA
INDT/R330B: VGA UXGA
Flexible parallel graphics controller and LC-display
interfaces:
12-bit (½ pixel/clock) – Tx only
18- / 24-bit (1 pixel/clock)
36- / 48-bit (2 pixel/clock)
Flexible pixel data clocking on rising/falling/both
clock edges
Pixel Clock frequency: 24 – 161 MHz
Easy adaptation to DVI and LDI/LVDS through
standard interface devices
4 channel audio interface (IEC958 compliant S/P-
DIF)
High- and low-speed bi-directional sideband data
channels
Single + 3.3 V power supply
Extended temperature range: -40 – +85 °C
Applications:
Long distance multimedia consoles
High resolution industrial remote terminals
Video broadcast systems
Long distance camera links
Machine vision systems
Car navigation & telematics systems
Digital TV equipment
Video Projectors
Home Cinemas
Chip
Max. resolution (VESA, 60 Hz)
and max. available video bandwidth
Video, Audio,
Sideband
Video, Audio
Video
INDT/R165B XGA 18-bit XGA 18-bit XGA 24-bit
INDT/R330B SXGA 24-bit UXGA 18-bit UXGA 18-bit
Typical Application:
PC
Graphics
Controller
Camera
DVD
HDTV
VIDEO Transmitter
Receiver
DATA
AUDIO
INDT165B
or
INDT330B
STP-cable
INDR165B
or
INDR330B
VIDEO
TFT
LC-Display
DATA
AUDIO
Date: 2005-02-18 Revision: 1.1
Page 1 of 41

1 page




INDT165B pdf
Data Sheet
INDT/R165B
INDT/R330B
The transmitter’s pixel interface accept pixel data with a pixel clock frequency of 24 – 161 MHz (full pixel mode). In single-
ended mode, PX_CLK+ is the clock input and PX_CLK– has to be tied to GND. All pixel data and pixel clock inputs of the
transmitter can be selected through the VREF-pin to either work with conventional graphic controllers with 3.3 V output
voltage swing or to work with latest controllers with low voltage swing (1.0 – 2.0 V, see Figure 3.3 VREF Reference
Circuitry). The pixel data and pixel clock outputs of the receiver provide a 3.3 V CMOS compliant output.
1.2.2 Pixel Interface Modes
The pixel interface is configurable to accommodate all the various graphic interface standards in the market. The width of
the pixel interface is a function of the selected operating mode.
In half-pixel mode the bit width of the pixel interface is 12-bit. In half-pixel mode the lower and upper 12 bits of a parallel
video interface (24-bit) are transmitted at consecutive sampling edges. This mode is supported only at the Tx devices.
In full-pixel mode the bit width of the pixel interface can be set to support an 18- or 24-bit wide parallel video interface.
1 pixel per sampling edge is transmitted.
In double-pixel mode the bit width of the pixel interface can be set to support a 36- or 48-bit wide parallel video
interface. 2 pixels per sampling edge are transmitted.
1.2.3 Pixel Clock Sampling Modes
The pixel interface can be set to support data sampling at the rising, falling or at both edges of the pixel clock,
depending on the selected mode.
Table 1.4 and Figure 1.3, Figure 1.4, Figure 1.5 summarize the various options for configuring the pixel interface.
Pixel Mode
12-bit
(Half Pixel)
TX Only
18-bit
(Full Pixel)
24-bit
(Full Pixel)
36-bit
(Double
Pixel)
Clock
Edge
both
both
rising
rising
rising
falling
both
rising
falling
both
rising
falling
PX_CLK+
↑↓
↑↓
↑↓
↑↓
48-bit
(Double
Pixel)
rising
falling
PX_CLK
Description
12 bits low part of pixel(n) @ rising edge of PX_CLK+
12 bits high part of pixel(n) @ falling edge of PX_CLK+
12 bits low part of pixel(n) @ falling edge of PX_CLK+
12 bits high part of pixel(n) @ rising edge of PX_CLK+
12 bits low part of pixel(n) @ rising edge of PX_CLK+
12 bits high part of pixel(n) @ rising edge of PX_CLK
12 bits low part of pixel(n) @ rising edge of PX_CLK
12 bits high part of pixel(n) @ rising edge of PX_CLK+
18 bits of pixel(n) sampled at rising edge of PX_CLK+
18 bits of pixel(n) sampled at falling edge of PX_CLK+
18 bits of pixel(n) sampled at both edges of PX_CLK+
24 bits of pixel(n) sampled at rising edge of PX_CLK+
24 bits of pixel(n) sampled at falling edge of PX_CLK+
24 bits of pixel(n) sampled at both edges of PX_CLK+
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at rising edge of PX_CLK+
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at falling edge of PX_CLK+
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at rising edge of PX_CLK+
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at falling edge of PX_CLK+
Table 1.4: Overview – Pixel Interface Configurations
Date: 2005-02-18 Revision: 1.1
Page 5 of 41

5 Page





INDT165B arduino
Data Sheet
INDT/R165B
INDT/R330B
1.4 Audio Interface
The audio interface provides four serial audio channels, which are compliant to the Standard IEC958 Digital audio interface
from the EBU (European Broadcasting Union), also known as S/P-DIF Interface. It supports sampling frequencies of 44,1
kHz and 48,0 kHz. The audio data interface can be disabled to free up bandwidth for pixel data transmission.
AI_C0
AI_C1
AI_C2
AI_C3
Audio
S/P DIF
Downstream
Audio
S/P DIF
INDT
Transmitter
INDR
Reveiver
Figure 1.7: Audio Interface
Signal
AI_C0
AI_C1
AI_C2
AI_C3
Tx Rx Description
IN OUT S/P-DIF Audio Channel 0
IN OUT S/P-DIF Audio Channel 1
IN OUT S/P-DIF Audio Channel 2
IN OUT S/P-DIF Audio Channel 3
Table 1.9: Audio Interface Signals
AI_C0
AI_C1
AI_C2
AI_C3
Date: 2005-02-18 Revision: 1.1
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