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PDF DM74S373 Data sheet ( Hoja de datos )
| Número de pieza | DM74S373 | |
| Descripción | (DM74S373 / DM74S374) 3-STATE Octal D-Type Transparent Latches | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1986
Revised May 2000
DM74S373 • DM74S374
3-STATE Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74S373 are transparent D-type
latches meaning that while the enable (G) is HIGH the Q
outputs will follow the data (D) inputs. When the enable is
taken LOW the output will be latched at the level of the
data that was set up.
The eight flip-flops of the DM74S374 are edge-triggered D-
type flip-flops. On the positive transition of the clock, the Q
outputs will be set to the logic states that were set up at the
D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines
simplify system design as ac and dc noise rejection is
improved by typically 400 mV due to the input hysteresis. A
buffered output control input can be used to place the eight
outputs in either a normal logic state (HIGH or LOW logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines signifi-
cantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs
are OFF.
Features
s Choice of 8 latches or 8 D-type flip-flops in a single
package
s 3-STATE bus-driving outputs
s Full parallel-access for loading
s Buffered control inputs
s P-N-P input reduce D-C loading on data lines
Ordering Code:
Order Number Package Number
Package Description
DM74S373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74S373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74S374WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74S374N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74S373N
© 2000 Fairchild Semiconductor Corporation DS006486
DM74S374N
www.fairchildsemi.com
1 page  
DM74S374 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
VOH
VOL
II
IH
IIL
IOZH
IOZL
IOS
ICC
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Off-State Output Current with
HIGH Level Output Voltage Applied
Off-State Output Current with
LOW Level Output Voltage Applied
Short Circuit Output Current
Supply Current
VCC = Min, II = −18 mA
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
VIH = Min, VIL = Max
VCC = Max, VI = 5.5V
VCC = Max, VI = 2.7V
VCC = Max, VI = 0.5V
VCC = Max, VO = 2.4V
VIH = Min, VIL = Max
VCC = Max, VO = 0.5V
VIH = Min, VIL = Max
VCC = Max (Note 14)
VCC = Max
Outputs HIGH
Outputs LOW
2.4
−40
Outputs Disabled
Note 13: All typicals are at VCC = 5V, TA = 25°C.
Note 14: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Typ
(Note 13)
3.2
90
Max
−1.2
0.5
1
50
−250
50
−50
−100
110
140
160
DM74S374 Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
fMAX
tPLH
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
tPZH Output Enable Time to
HIGH Level Output
tPZL Output Enable Time to
LOW Level Output
tPHZ Output Disable Time from
HIGH Level Output (Note 15)
tPLZ Output Disable Time from
LOW Level Output (Note 15)
Note 15: CL = 5 pF
From (Input)
To (Output)
Clock to Any Q
Clock to Any Q
Output Control to Any Q
Output Control to Any Q
Output Control to Any Q
Output Control to Any Q
RL = 280Ω
CL = 15 pF
CL = 50 pF
Min Max Min Max
75 75
15 15
17 20
15 17
18 23
9
12
Units
V
V
V
mA
µA
µA
µA
µA
mA
mA
Units
MHz
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet DM74S373.PDF ] | |
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