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PDF UT54ACTS109 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACTS109 | |
| Descripción | Radiation-Hardened Dual J-K Flip-Flops | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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UT54ACS109/UT54ACTS109
Radiation-Hardened
Dual J-K Flip-Flops
FEATURES
• radiation-hardened CMOS
- Latchup immune
• High speed
• Low power consumption
• Single 5 volt supply
• Available QML Q or V processes
• Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K posi-
tive triggered flip-flops. A low level at the preset or clear inputs
sets or resets the outputs regardless of the other input levels.
When preset and clear are inactive (high), data at the J and K
input meeting the setup time requirements are transferred to the
outputs on the positive-going edge of the clock pulse. Following
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
PRE
L
H
L
H
H
H
H
H
INPUTS
CLR
CLK
HX
LX
LX
H
H
H
H
HL
OUTPUT
JK Q
Q
XX H
L
XX
L
H
X X H1 H1
LL
L
H
HL
Toggle
L H No Change
HH H
L
X X No Change
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for VOH if the lows at preset and clear are near VIL maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
PINOUTS
16-Pin DIP
Top View
CLR1
J
K1
CLK1
PRE1
Q1
Q1
VSS
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
CLR1
J1
K1
CLK1
PRE1
Q1
Q1
VSS
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
PRE1
J1
CLK1
K1
CLR1
(5)
(2)
(4)
(3)
(1)
S
J1
C1
K1
R
(6) Q1
(7)
Q1
(11)
PRE2
(14)
J2
(12)
CLK2
(13)
K2
(15)
CLR2
(10)
Q2
(9) Q2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
61 RadHard MSI Logic
1 page  
UT54ACS109/UT54ACTS109
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
65 RadHard MSI Logic
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet UT54ACTS109.PDF ] | |
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