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PDF FM3164 Data sheet ( Hoja de datos )
| Número de pieza | FM3164 | |
| Descripción | (FM3104 - FM31256) Integrated Processor Companion | |
| Fabricantes | Ramtron | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de FM3164 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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FM3104/16/64/256
Integrated Processor Companion with Memory
Features
High Integration Device Replaces Multiple Parts
• Serial Nonvolatile Memory
• Real-time Clock (RTC)
• Low Voltage Reset
• Watchdog Timer
• Early Power-Fail Warning/NMI
• Two 16-bit Event Counters
• Serial Number with Write-lock for Security
Ferroelectric Nonvolatile RAM
• 4Kb, 16Kb, 64Kb, and 256Kb versions
• Unlimited Read/Write Endurance
• 10 year Data Retention
• NoDelay™ Writes
Real-time Clock/Calendar
• Backup Current under 1 µA
• Seconds through Centuries in BCD format
• Tracks Leap Years through 2099
• Uses Standard 32.768 kHz Crystal (6pF)
• Software Calibration
• Supports Battery or Capacitor Backup
Description
The FM31xxx is a family of integrated devices that
includes the most commonly needed functions for
processor-based systems. Major features include
nonvolatile memory available in various sizes, real-
time clock, low-VDD reset, watchdog timer,
nonvolatile event counter, lockable 64-bit serial
number area, and general purpose comparator that
can be used for an early power-fail (NMI) interrupt or
other purpose. The family operates from 2.7 to 5.5V.
Each FM31xxx provides nonvolatile RAM available
in sizes including 4Kb, 16Kb, 64Kb, and 256Kb
versions. Fast write speed and unlimited endurance
allow the memory to serve as extra RAM or
conventional nonvolatile storage. This memory is
truly nonvolatile rather than battery backed.
The real-time clock (RTC) provides time and date
information in BCD format. It can be permanently
powered from external backup voltage source, either
a battery or a capacitor. The timekeeper uses a
common external 32.768 kHz crystal and provides a
calibration mode that allows software adjustment of
timekeeping accuracy.
This is a product in development. Characteristic data
and other specifications are subject to change without notice.
Rev 0.2
May 2003
Processor Companion
• Active-low Reset Output for VDD and Watchdog
• Programmable VDD Reset Trip Point
• Manual Reset Filtered and De-bounced
• Programmable Watchdog Timer
• Dual Battery-backed Event Counter Tracks
System Intrusions or other Events
• Comparator for Early Power-Fail Interrupt
• 64-bit Programmable Serial Number with Lock
Fast Two-wire Serial Interface
• Up to 1 MHz Maximum Bus Frequency
• Supports Legacy Timing for 100 kHz & 400 kHz
• Device Select Pins for up to 4 Memory Devices
• RTC, Supervisor Controlled via 2-wire Interface
Easy to Use Configurations
• Operates from 2.7 to 5.5V
• Small Footprint 14-pin SOIC
• Low Operating Current
• -40°C to +85°C Operation
The processor companion includes commonly needed
CPU support functions. Supervisory functions
include a reset output signal controlled by either a
low VDD condition or a watchdog timeout. /RST
goes active when VDD drops below a programmable
threshold and remains active for 100 ms after VDD
rises above the trip point. A programmable watchdog
timer runs from 100 ms to 3 seconds. The watchdog
timer is optional, but if enabled it will assert the reset
signal for 100 ms if not restarted by the host before
the timeout. A flag-bit indicates the source of the
reset.
A general-purpose comparator compares an external
input pin to the onboard 1.2V reference. This is
useful for generating a power-fail interrupt (NMI) but
can be used for any purpose. The family also includes
a programmable 64-bit serial number that can be
locked making it unalterable. Additionally it offers a
dual battery-backed event counter that tracks the
number of rising or falling edges detected on
dedicated input pins.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 22
1 page  
The watchdog timer can also be used to assert the
reset signal (/RST). The watchdog is a free running
programmable timer. The period can be software
programmed from 100 ms to 3 seconds in 100 ms
increments via a 5-bit nonvolatile register. All
programmed settings are minimum values and vary
with temperature according to the operating
specifications. The watchdog has two additional
controls associated with its operation, a watchdog
enable bit (WDE) and timer restart bits (WR). Both
the enable bit must be set and the watchdog must
timeout in order to drive /RST active. If a reset event
occurs, the timer will automatically restart on the
rising edge of the reset pulse. If not enabled, the
watchdog timer runs but has no effect on /RST. Note
that setting the maximum timeout setting (11111b)
disables the counter to save power. The second
control is a nibble that restarts the timer preventing a
reset. The timer should be restarted after changing the
timeout value.
The watchdog timeout value is located in register
0Ah, bits 4-0, and the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 09h. Writing this pattern
will also cause the timer to load new timeout values.
Writing other patterns to this address will not affect
its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
timer as described above. This assures that the full
timeout period will be set immediately after enabling.
The watchdog is disabled when VDD is below VTP.
The following table summarizes the watchdog bits. A
block diagram follows.
Watchdog timeout
Watchdog enable
Watchdog restart
WDT4-0
WDE
WR3-0
0Ah, bits 4-0
0Ah, bit 7
09h, bits 3-0
100 ms
clock
Timebase
WR3-0 = 1010b to restart
Counter
/RST
Watchdog
timeout
WDE
Figure 3. Watchdog Timer
Manual Reset
The /RST pin is bi-directional and allows the
FM31xxx to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms.
Rev 0.2
May 2003
FM3104/16/64/256
MCU
RST
Reset
Switch
FM31xxx
Switch
Behavior
RST
FM31xxx
drives
100 ms
Figure 4. Manual Reset
Note that an internal weak pull-up on /RST
eliminates the need for additional external
components.
Reset Flags
In case of a reset condition, a flag will be set to
indicate the source of the reset. A low VDD reset is
indicated by the POR flag, register 09h bit 6. A
watchdog reset is indicated by the WTR flag, register
09h bit 7. A manual reset will result in no flag being
set, so the absence of a flag is a manual reset. Note
that the flags are internally set in response to reset
sources, but they must be cleared by the user. When
the register is read, it is possible that both flags are
set if both have occurred since the user last cleared
them.
Early Power Fail Comparator
An early power fail warning can be provided to the
processor well before VDD drops out of spec. The
comparator is used to create a power fail interrupt
(NMI). This can be accomplished by connecting the
PFI pin to the unregulated power supply via a resistor
divider. An application circuit is shown below. The
voltage on the PFI input pin is compared to an
onboard 1.2V reference. When the PFI input voltage
drops below this threshold, the comparator will drive
the CAL/PFO pin to a low state. The comparator has
300 mV (nominal) of hysteresis to reduce noise
sensitivity.
Regulator
VDD
FM31xxx
To MCU CAL/PFO
NMI input
+
- 1.2V ref
PFI
Figure 5. Comparator as Early Power-Fail Warning
Page 5 of 22
5 Page 
FM3104/16/64/256
0Ch
RC
CC
C2P
C1P
Event Counter Control
D7 D6
D5
D4
D3
D2
D1
D0
--
-
- RC CC C2P C1P
Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the
values without missing count events. The RC bit will be automatically cleared.
Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by
C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of
Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P has no
effect when CC=1. Battery-backed, read/write.
CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P has no effect when CC=1. Battery-
backed, read/write.
CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. Battery-backed, read/write.
0Bh
SNL
WP1-0
Companion Control
D7 D6
D5
D4
D3
D2
D1
D0
SNL -
-
WP1
WP0
VBC
VTP1
VTP0
Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only. SNL cannot be
cleared once set to 1. Nonvolatile, read/write.
Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write.
VBC
VTP1-0
Write protect addresses WP1 WP0
None
00
Bottom 1/4
01
Bottom 1/2
10
Full array
11
VBAK Charger Control. Setting VBC to 1 causes a 4 µA trickle charge current to be supplied on VBAK. Clearing
VBC to 0 disables the charge current. Nonvolatile, read/write.
VTP select. These bits control the reset trip point for the low VDD reset function. Nonvolatile, read/write.
VTP
2.6V
2.9V
3.9V
4.4V
VTP1
0
0
1
1
VTP0
0
1
0
1
0Ah
WDE
WDT4-0
Watchdog Control
D7 D6
D5
D4
D3
D2
D1
D0
WDE
-
-
WDT4
WDT3
WDT2
WDT1
WDT0
Watchdog Enable. When WDE=1 the watchdog timer can cause the /RST signal to go active. When WDE = 0 the
timer runs but has no effect on /RST. Note as the timer is free-running, users should restart the timer using WR3-0
prior to setting WDE=1. This assures a full watchdog timeout interval occurs. Nonvolatile, read/write.
Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog
timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write.
Watchdog timeout
Invalid – default 100 ms
100 ms
200 ms
300... ms
2000 ms
2100 ms
220...0 ms
2900 ms
3000 ms
Disable counter
WDT4 WDT3 WDT2 WDT1 WDT0
0 00 00
0 00 01
0 00 10
0 00 11
1 01 00
1 01 01
1 01 10
1 11 01
1 11 10
1 11 11
Rev 0.2
May 2003
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet FM3164.PDF ] | |
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