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PDF W982508AH Data sheet ( Hoja de datos )

Número de pieza W982508AH
Descripción 8M X 4 BANKS X 8 BIT SDRAM
Fabricantes Winbond 
Logotipo Winbond Logotipo



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W982508AH
GENERAL DESCRIPTION
8M × 4 BANKS × 8 BIT SDRAM
W982508AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
8M words × 4 banks × 8 bits. Using pipelined architecture and 0.175 µm process technology,
W982508AH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the
personal computer industrial standard, W982508AH is sorted into three speed grades: -7, -75 and -
8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the
PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W982508AH is ideal for main memory in
high performance applications.
FEATURES
3.3V ±0.3V Power Supply
Up to 143 MHz Clock Frequency
8,388,608 Words × 4 Banks × 8 Bits Organization
Auto Refresh and Self Refresh
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and Full Page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Power-down Mode
Auto-precharge and Controlled Precharge
4K Refresh Cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil - 0.80
KEY PARAMETERS
SYM.
DESCRIPTION
tCK Clock Cycle Time
tAC Access Time from CLK
tRP Precharge to Active Command
tRCD Active to Read/Write Command
ICC1 Operation Current (Single bank)
ICC4 Burst Operation Current
ICC6 Self-refresh Current
MIN.
/MAX.
Min.
Max.
Min.
Min.
Max.
Max.
Max.
-7
(PC133, CL2)
7 nS
5.4 nS
15 nS
15 nS
80 mA
100 mA
3 mA
-75
(PC133, CL3)
7.5 nS
5.4 nS
20 nS
20 nS
75 mA
95 mA
3 mA
-8H
(PC100)
8 nS
6 nS
20 nS
20 nS
70 mA
90 mA
3 mA
Publication Release Date: December 2000
- 1 - Revision A1

1 page




W982508AH pdf
W982508AH
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Input, Output Voltage
VIN, VOUT
-0.3VCC +0.3
V
1
Power Supply Voltage
VCC, VCCQ
-0.34.6
V
1
Operating Temperature
TOPR
070
°C 1
Storage Temperature
TSTG
-55150
°C
1
Soldering Temperature (10s)
TSOLDER
260
°C 1
Power Dissipation
PD 1 W 1
Short Circuit Output Current
IOUT
50 mA 1
Note 1: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C)
PARAMETER
SYMBOL MIN. TYP.
Power Supply Voltage
Power Supply Voltage (for I/O
Buffer)
VCC
VCCQ
3.0 3.3
3.0 3.3
Input High Voltage
Input Low Voltage
VIH 2.0 -
VIL -0.3 -
Note 2: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS
VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS
MAX.
3.6
3.6
VCC +0.3
0.8
UNIT
V
V
V
V
NOTES
2
2
2
2
CAPACITANCE
(VCC = 3.3V, f = 1 MHz, TA = 25°C)
PARAMETER
Input Capacitance
(A0 to A12, BS0, BS1, CS , RAS , CAS , WE , LDQM,
UDQM, CKE)
Input Capacitance (CLK)
Input/Output capacitance
Note: These parameters are periodically sampled and not 100% tested.
SYMBOL
CI
CCLK
CIO
MIN.
-
-
-
MAX.
3.8
3.5
6.5
UNIT
pf
pf
pf
Publication Release Date: December 2000
- 5 - Revision A1

5 Page





W982508AH arduino
W982508AH
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS
and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequential mode.
Burst Write Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding
RAS high at the rising edge of the clock. The address inputs determine the starting column address.
Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst
read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write
operation, then any residual data from the burst write cycle will be ignored.
- 11 -
Publication Release Date: December 2000
Revision A1

11 Page







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