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PDF IDT74LVC2244A Data sheet ( Hoja de datos )

Número de pieza IDT74LVC2244A
Descripción CMOS OCTAL BUFFER/DRIVER
Fabricantes IDT 
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IDT74LVC2244A Hoja de datos, Descripción, Manual
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IDT74LVC2244A
3.3V CMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
3.3V CMOS OCTAL
BUFFER/DRIVER WITH 3-
STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
INDUSTRIALTEMPERATURERANGE
IDT74LVC2244A
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-rail output swing for increased noise margin
• All inputs, outputs, and I/O are 5V tolerant
• Available in SOIC, SSOP, QSOP, and TSSOP packages
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
This octal buffer/driver is built using advanced dual metal CMOS
technology. The LVC2244A device is organized as two 4-bit line drivers
with separate output-enable (OE) inputs. When OE is low, the device
passes data from the A inputs to the Y outputs. When OE is high, the outputs
are in the high-impedance state.
To ensure the high-impedance state during power up or power down,
OE should be tied to Vcc through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking capability of the driver.
The LVC2244A has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver
has been designed to drive ±12mA at the designated threshold levels.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
FUNCTIONAL BLOCK DIAGRAM
1OE 1
1A1 2
1A2 4
1A3 6
1A4 8
18 1Y1
16 1Y2
14
1Y3
12 1Y4
19
2OE
2A1 11
2A2 13
2A3 15
2A4 17
9 2Y1
7 2Y2
5
2Y3
3 2Y4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2000 Integrated Device Technology, Inc.
1
FEBRUARY 2000
DSC-4644/1

1 page

IDT74LVC2244A pdf
IDT74LVC2244A
3.3V CMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
VCC
VLOAD
Open
VIN
Pulse (1, 2)
Generator
VOUT
D.U.T.
500GND
RT
500
CL
Test Circuit for All Outputs
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.
2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
LVC Link
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
VLOAD
tPZH
OUTPUT SWITCH
NORMALLY GND
HIGH
VLOAD/2
VT
tPHZ
VT
0V
VIH
VT
0V
VLOAD/2
VOL+VLZ
VOL
VOH
VOH-VHZ
0V
LVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tREM
tSU tH
Set-up, Hold, and Release Times
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
LOW-HIGH-LOW
PULSE
tW
HIGH-LOW-HIGH
PULSE
Pulse Width
VT
VT
LVC Link
5

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