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Número de pieza | MAX1394 | |
Descripción | (MAX1391 / MAX1394) 1-Channel True-Differential/ 2-Channel Single-Ended | |
Fabricantes | Maxim Integrated Products | |
Logotipo | ||
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19-3720; Rev 0; 11/06
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
General Description
The MAX1391/MAX1394 micropower, serial-output,
8-bit, analog-to-digital converters (ADCs) operate with a
single power supply from +1.5V to +3.6V. These ADCs
feature automatic shutdown, fast wake-up, and a high-
speed 3-wire interface. Power consumption is only
0.743mW (VDD = +1.5V) at the maximum conversion
rate of 416ksps. AutoShutdown™ between conversions
reduces power consumption at slower throughput rates.
The MAX1391/MAX1394 require an external reference
VREF that has a wide range from 0.6V to VDD. The
MAX1391 provides one true-differential analog input
that accepts signals ranging from 0 to VREF (unipolar
mode) or ±VREF/2 (bipolar mode). The MAX1394 pro-
vides two single-ended inputs that accept signals rang-
ing from 0 to VREF. Analog conversion results are
available through a 5MHz 3-wire SPI™-/QSPI™-/
MICROWIRE™-/digital signal processor (DSP)-compati-
ble serial interface. Excellent dynamic performance,
low voltage, low power, ease of use, and small pack-
age sizes make these converters ideal for portable bat-
tery-powered data-acquisition applications, as well as
other applications that demand low-power consumption
and minimal space.
The MAX1391/MAX1394 are available in a space-sav-
ing (3mm x 3mm), 10-pin TDFN package. The parts
operate over the extended (-40°C to +85°C) and mili-
tary (-55°C to +125°C) temperature ranges.
Applications
Portable Datalogging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Process Control
Features
o 416ksps, 8-Bit Successive-Approximation
Register (SAR) ADCs
o Single True-Differential Analog Input Channel
with Unipolar-/Bipolar-Selected Input (MAX1391)
o Dual Single-Ended Input Channel with Channel-
Selected Input (MAX1394)
o ±0.2 LSB INL, ±0.2 LSB DNL, No Missing Codes
o ±0.25 LSB Total Unadjusted Error (TUE)
o 49dB SINAD at 100kHz Input Frequency
o Single-Supply Voltage (+1.5V to +3.6V)
o 0.97mW at 416ksps, 1.8V
o 0.230mW at 100ksps, 1.8V
o 3.1µW at 1ksps, 1.8V
o < 1µA Shutdown Current
o External Reference (0.6V to VDD)
o AutoShutdown Between Conversions
o SPI-/QSPI-/MICROWIRE-/DSP-Compatible,
3- or 4-Wire Serial Interface
o Small (3mm x 3mm), 10-Pin TDFN
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information
PART
MAX1391ETB
MAX1391MTB**
MAX1394ETB
MAX1394MTB**
TEMP RANGE
-40°C to +85°C
-55°C to +125°C
-40°C to +85°C
-55°C to +125°C
PIN-PACKAGE
10 TDFN-EP*
10 TDFN-EP*
10 TDFN-EP*
10 TDFN-EP*
ANALOG INPUTS
1-CH DIFF
1-CH DIFF
2-CH S/E
2-CH S/E
TOP MARK
AOX
—
APA
—
PKG CODE
T1033-1
T1033-1
T1033-1
T1033-1
*EP = Exposed pad.
**Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page www.DataSheet4U.com
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
UNI/BIP OR
CH1/CH2
OE
CS
SCLK
tCHS
tUBS
tCHH
tUBH
tCSO tCSS
tDOE
tCL tCH
tCP
DOUT
HIGH-Z
Figure 1. Detailed Serial-Interface Timing Diagram
tDOV
tOEW
tCSW
tDOD
HIGH-Z
VDD
DOUT
6kΩ
DOUT
6kΩ 50pF
50pF
GND
a) HIGH IMPEDANCE TO VOH, VOL TO VOH,
AND VOH TO HIGH IMPEDANCE
GND
b) HIGH IMPEDANCE TO VOL, VOH TO VOL,
AND VOL TO HIGH IMPEDANCE
Figure 2. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________ 5
5 Page www.DataSheet4U.com
1.5V to 3.6V, 416ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 8-Bit, SAR ADCs
AutoShutdown Mode
The ADC automatically powers down on the SCLK
falling edge that clocks out the LSB. This is the falling
edge after the 11th SCLK. DOUT goes low when the
LSB has been clocked into the master (µC) on the 16th
rising SCLK edge.
Alternatively, drive OE high to force the MAX1391/
MAX1394 into power-down. Whenever OE goes high,
the ADC powers down and disables DOUT regardless
of CS, SCLK, or the state of the ADC. DOUT enters a
high-impedance state after tDOD.
External Reference
The MAX1391/MAX1394 use an external reference
between 0.6V and (VDD + 50mV). Bypass REF with a
I/O
SCK
MISO
I/O
a) SPI
OE
CS
SCLK MAX1391
MAX1394
DOUT
UNI/BIP
(CH1/CH2)*
CS OE
CS
SCK SCLK MAX1391
MAX1394
MISO
I/O
DOUT
UNI/BIP
(CH1/CH2)*
b) QSPI
I/O OE
CS
SK SCLK MAX1391
MAX1394
SI DOUT
I/O UNI/BIP
(CH1/CH2)*
c) MICROWIRE
*INDICATES THE MAX1394
Figure 7. Common Serial-Interface Connections to the
MAX1391/MAX1394
0.1µF capacitor to GND for best performance (see the
Typical Operating Circuit).
Serial Interface
The MAX1391/MAX1394 serial interface is fully compati-
ble with SPI, QSPI, and MICROWIRE (see Figure 7). If a
serial interface is available, set the µC’s serial interface
in master mode so the µC generates the serial clock.
Choose a clock frequency between 100kHz and 5MHz.
CS and OE can be connected together and driven
simultaneously. OE can also be connected to GND if the
DOUT bus is not shared and driven independently.
SPI and MICROWIRE
When using SPI or MICROWIRE, make the µC the bus
master and set CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1. (These are the bits in the SPI or
MICROWIRE control register.) Two consecutive 1-byte
reads are required to get the entire 8-bit result from the
ADC. The MAX1391/MAX1394 shut down after clocking
out the LSB. DOUT then becomes high impedance.
DOUT transitions on SCLK’s falling edge and is
clocked into the µC on the SCLK’s rising edge. See
Figure 7 for connections and Figures 8 and 9 for timing
diagrams. The conversion result contains 4 zeros, fol-
lowed by the 8 data bits with the data in MSB-first for-
mat. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the MSB of the data is clocked into the
µC on the SCLK’s fifth rising edge. To be compatible
with SPI and MICROWIRE, connect CS and OE togeth-
er and drive simultaneously.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 8 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1391/MAX1394 require a minimum of 12
clock cycles from the µC to clock out the 8 bits of data.
See Figure 7 for connections and Figures 8 and 9 for
timing diagrams. The conversion result contains 4
zeros, followed by the 8 data bits with the data in MSB-
first format. The MAX1391/MAX1394 shut down after
clocking out the LSB. DOUT then becomes high imped-
ance. When using CPOL = 0 and CPHA = 0 or CPOL =
1 and CPHA = 1, the MSB of the data is clocked into
the µC on the SCLK’s fifth rising edge. To be compati-
ble with QSPI, connect CS and OE together and drive
simultaneously.
DSP Interface
Figure 10 shows the timing for DSP operation. Figure
11 shows the connections between the MAX1391/
MAX1394 and several common DSPs.
______________________________________________________________________________________ 11
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet MAX1394.PDF ] |
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