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PDF ISL22419 Data sheet ( Hoja de datos )
| Número de pieza | ISL22419 | |
| Descripción | Single Digitally Controlled Potentiometer | |
| Fabricantes | Intersil Corporation | |
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ISL22419
® Single Digitally Controlled Potentiometer (XDCP™)
Data Sheet
June 28, 2006
FN6311.0
Low Noise, Low Power, SPI® Bus, 128 Taps,
Wiper Only
The ISL22419 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the content of the
DCP’s IVR to the WR.
The DCP can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.
Pinout
ISL22419
(8 LD MSOP)
TOP VIEW
SCK
SDO
SDI
CS
1
2
3
4
8 Vcc
7 RW
6 SHDN
5 GND
Features
• 128 resistor taps
• SPI serial interface
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ 55 °C
• 8 Lead MSOP
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(kΩ)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL22419UFU8Z
(Notes 1, 2)
419UZ
50
-40 to +125
8 Ld MSOP
M8.118
(Pb-Free)
ISL22419WFU8Z
(Notes 1, 2)
419WZ
10
-40 to +125
8 Ld MSOP
M8.118
(Pb-Free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL22419
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 5)
Hysteresis SHDN, SCK, SDI, and CS Input Buffer
Hysteresis
VOL
Rpu
(Note 13)
SDO Output Buffer LOW Voltage
SDO Pull-up Resistor Off-chip
IOL = 4mA
Maximum is determined by tRO and tFO with
maximum bus load Cbus = 30pF, fSCK =
5MHz
0.05*
VCC
0
Cpin SHDN, SCK, SDI, SDO and CS Pin
(Note 14) Capacitance
fSCK
tCYC
tWH
tWL
tLEAD
tLAG
tSU
tH
tRI
tFI
tDIS
tV
tHO
tRO
tFO
tCS
SPI Frequency
SPI Clock Cycle Time
SPI Clock High Time
SPI Clock Low Time
Lead Time
Lag Time
SDI, SCK and CS Input Setup Time
SDI, SCK and CS Input Hold Time
SDI, SCK and CS Input Rise Time
SDI, SCK and CS Input Fall Time
SDO Output Disable Time
SDO Output Valid Time
SDO Output Hold Time
SDO Output Rise Time
SDO Output Fall Time
CS Deselect Time
Rpu = 2k, Cbus = 30pF
Rpu = 2k, Cbus = 30pF
200
100
100
250
250
50
50
10
10
0
0
2
MAX
0.4
2
10
5
20
100
350
60
60
UNIT
V
V
kΩ
pF
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Notes:
5. Typical values are for TA = 25°C and 3.3V supply voltage.
6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)0/LSB.
8. FS error = [V(RW)127 – VCC]/LSB.
9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
10. INL = [V(RW)i – (i • LSB) – V(RW)0]/LSB for i = 1 to 127
11.
TCV
=
-------M-----a----x----(--V----(---R-----W------)--i--)---–-----M-----i--n----(--V-----(--R-----W------)--i--)------ × ----1---0----6----- for i = 16 to 127 decimal, T = -40°C to 125°C. Max( ) is the maximum value of the wiper
[Max(V(RW)i) + Min(V(RW)i)] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
12. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.
13. Rpu is specified for the highest data rate transfer for the device. Higher value pullup can be used at lower data rates.
14. This parameter is not 100% tested.
5 FN6311.0
June 28, 2006
5 Page 
ISL22419
CS
SCK
SDI
0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0
0 D6 D5 D4 D3 D2 D1 D0
FIGURE 12. THREE BYTE WRITE SEQUENCE
CS
SCK
SDI
SDO
0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0
Don’t Care
0 D6 D5 D4 D3 D2 D1 D0
FIGURE 13. THREE BYTE READ SEQUENCE
Applications Information
Communicating with ISL22419
Communication with ISL22419 proceeds using SPI interface
through the ACR (address 11b), IVR (address 00b) and WR
(address 00b) registers.
The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to this
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit (ACR[7]) at address 11b to 1.
The non-volatile IVR stores the power up value of the wiper.
IVR is accessible when MSB bit (ACR[7]) at address 11b is
set to 0. Writing a new value to the IVR register will set a
new power up position for the wiper. Also, writing to this
register will load the same value into the WR as the IVR.
Reading from the IVR will not change the WR, if its contents
are different.
The typical application diagram is shown in Figure 14. For
proper operation adding 0.1µF decoupling ceramic capacitor
to VCC is recommended. The capacitor value may vary
based on expected noise frequency of the design.
11 FN6311.0
June 28, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL22419.PDF ] | |
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