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PDF DP83231 Data sheet ( Hoja de datos )
| Número de pieza | DP83231 | |
| Descripción | CRD Device | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
February 1991
DP83231 CRDTM Device
(FDDI Clock Recovery Device)
General Description
The DP83231 CRD device is a clock recovery device that
has been designed for use in 100 Mbps FDDI (Fiber Distrib-
uted Data Interface) networks The device receives serial
data from a Fiber Optic Receiver in differential ECL NRZI
4B 5B group code format and outputs resynchronized NRZI
received data and a 125 MHz received clock in differential
ECL format for use by the DP83251 55 PLAYERTM device
Features
Y Clock recovery at 100 Mbps data rate
Y Internal 250 MHz VCO
0 1% VCO operating range
Crystal controlled
Y Precision window centering delay line
Y Single a5V supply
Y 28-pin PLCC package
Y BiCMOS processing
FIGURE 1-1 FDDI Chip Set Block Diagram
TL F 10384 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
BSITM BMACTM PLAYERTM CDDTM and CRDTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10384
RRD-B30M105 Printed in U S A
1 page  
2 0 Functional Description (Continued)
FIGURE 2-1 DP83231 Block Diagram
28-Pin PLCC Package
TL F 10384 – 3
TL F 10384 – 2
Order Number DP83231AV
See NS Package Number V28A
FIGURE 2-2 DP83231 Pinout
TL F 10384 – 4
FIGURE 2-3 System Connection Diagram
5
5 Page 
5 0 Detailed Information
5 1 SPECIAL EXTERNAL COMPONENTS
Crystals
Manufacturer Nel Frequency Controls (414) 763-3591
Part C5400N
Manufacturer Standard Crystal Corporation
(818) 443-2121
Part 800R-A-10 41667-32
Key Specifications
Center Frequency 10 41667 MHz
Load Capacitance CL 32 pF
Frequency Calibration g20 PPM
Frequency Stability
(0 C –70 C)
g20 PPM
Aging
k g10 PPM
Pullability
either a motional capacitance of
t0 021
or
a change of at least 100 PPM when
the CL is changed from 32 pF to 18 pF
and a change of b100 PPM when the
CL is changed from 32 pF to 50 pF
Varactors
Manufacturer Alpha Industries (617) 935-5150
Part DKV6510-71
Key Specifications
Capacitance
Vr e 1V C l 85 pF
Vr e 4V 15 pF k C k 30 pF
5 2 LAYOUT RECOMMENDATIONS
The part should be bypassed between the EXTVCC and
EXTGND as close to the chip as possible (preferably under
the chip using chip caps) The part should also be bypassed
between the DVCC and DGND and the AVCC and AGND as
close to the chip as possible
No TTL logic lines should pass through the crystal OSC
FLTRs or VCO FLTR circuitry areas to avoid the possibility
of noise due to crosstalk
The crystal OSC FLTRs and the VCO FLTR circuitries
should be connected to Ground on isolated branches off of
the DGND pin If using a multilayered board with dedicated
VCC and Ground planes ensure that for the ground plane
that the ceramic resonator OSC FLTRs and the VCO FLTR
circuitries have their own small isolated islands that are con-
nected to the DGND and AGND pins as described above
The DVCC and AVCC pins should be connected to VCC on
an isolated branches off of the EXTVCC pin preferably be-
ing connected through a ferrite bead or a small inductor
The DGND and AGND pins should be connected to GND
on an isolated branches off of the EXTGND pin Connection
to the ground plane should be made only at the EXTGND
pin
This drawing was done with convenience in mind
FIGURE 5-1 Recommended Layout
11
TL F 10384 – 10
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DP83231.PDF ] | |
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