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PDF U2733B-C Data sheet ( Hoja de datos )

Número de pieza U2733B-C
Descripción Fractional-N Frequency Synthesizer
Fabricantes TEMIC Semiconductors 
Logotipo TEMIC Semiconductors Logotipo



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U2733B-C
Fractional-N Frequency Synthesizer for DAB Tuner
Description
The U2733B-C is a monolithically integrated
fractional-N frequency synthesizer circuit fabricated in
TEMIC’s advanced UHF5S technology. Designed for
applications in DAB receivers, it controls a VCO to
synthesize frequencies in the range of 70 to 500 MHz in
a 16 kHz raster; four different reference divide factors can
be selected. The lock status of the phase detector is
indicated at a special output pin, six switching outputs can
be addressed. An internal frequency doubler provides an
output signal having twice the frequency of the reference
oscillator. All functions of this IC are controlled by
I2C bus.
Features
D Microprocessor controlled via I2C bus
D 4 addresses selectable
D Four reference divide factors selectable:
1024, 1120, 1152, 1536
D Effectively
D Programmable 15-bit counter 1:2048 to 1:32767
effectively
D Three state phase detector with programmable charge
pump
D Superior phase noise performance
D Deactivation of tuning output programmable
D 6 switching outputs (open collector)
D Reference frequency doubler (open collector output)
D Lock status indication (open collector)
D Fully compatible to U2753B-C
D SSO20 package
Block Diagram
REF
NREF
4
5
RF
NRF
18
17
Frequency doubler
x2
FDO NFDO
10 9
Reference counter
Fractional N
control
Prog.
13 Bit counter
N/N=1
Three State
Phase
Detector
Lock detector
Prog.
charge pump
4 Bit latch
3
PLCK
1
PD
2
VD
7 Bit latch
2 Bit
latch
5 Bit latch
I2C Bus –Interface / Control
MUX
MUX
Switches
19 20
GND VS
67
8 11 12 13 14 15 16
ADR
SCL
SDA
SWC SWD SWE SWF SWG SWH
12476
Figure 1. Block diagram
TELEFUNKEN Semiconductors
Rev. A1, 21-Aug-96
Preliminary Information
1 (14)

1 page




U2733B-C pdf
U2733B-C
I2C Bus Instruction Codes
ÁÁÁÁÁÁÁADDDCCCÁÁÁÁÁÁÁooodiiivvvnnndiiitttrdddÁÁÁÁÁÁÁrrreeeeooosDrrrlllsebbbbbbÁÁÁÁÁÁÁbsyyyyyyyctttttttreeeeeeeiÁÁÁÁÁÁÁp123123tioÁÁÁÁÁÁÁn ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁMOXXXF101SÁÁÁÁÁÁÁDB ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ2RIXXXD10FÁÁÁÁÁÁÁD1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSRnWnD00015ÁÁÁÁÁÁÁ1C2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSnOWnX0014S0ÁÁÁÁÁÁÁD ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSWnnXT0093ÁÁÁÁÁÁÁE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSATnWnn0RS1824ÁÁÁÁÁÁÁ1IF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁSIAn1Wnn0S107132GÁÁÁÁÁÁÁ0 ÁÁÁÁÁÁÁSÁÁÁÁÁÁÁLInWnn5S001600B2HÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
I2C Bus Functions
I2C Bus Data Transfer
AS1, AS2 define the I2C bus address
Format
RD1, RD2 define the effective scaling factor of the
reference divider:
START – ADR – ACK – <instruction set> – STOP
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁRD1
RD2
Effective
The <instruction set> consists of a sequence of divider
Scaling
bytes and control bytes each followed by ACK. Divider
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFactor
byte i must be followed by divider byte i+1 (control byte
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0 0 1120 1 if i = 3) or the instruction set must be finished. Control
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ1 0 1152 bytes have to be handled accordingly.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0 1 1024
1
1
1536
Examples
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁni effective scaling factor (SFeff) of the main START–ADR–ACK–DB1–ACK–DB2–ACK–DB3
divider
SFeff = SUM(ni 2i)
– ACK – CB1 – ACK – CB2 –ACK – CB3 – ACK – STOP
OS OS = ‘H’ switches off tuning output
START – ADR – ACK – CB1 – ACK – CB2 – ACK –
T for T = ‘H’ reference signals describing the STOP
output frequencies of reference reference divider
and programmable divider are monitored at SWF However
(prog. div.) and SWC (ref. div.)
TRI TRI = ‘H’ switches off charge pump
I50, I100 define the charge pump current:
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁI50 I100 Charge Pumup Current
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(nominal)/A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ’L’ ’L’
50
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ’H’ ’L’
102
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ’L’ ’H’
151
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ’H’ ’H’
203
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁOFD OFD = ‘H’ switches off frequency doubler
START – ADR – ACK – DB1 – ACK – CB1 –ACK –
STOP
is not allowed.
Description
START
start condition
STOP
stop condition
ACK
acknoledge
ADR
address byte
2IFD
2IFD = ‘H’ doubles the frequency doubler output
current
DBi
divider byte i (i = 1, 2, 3)
SWa SWa = ‘H’ switches on output current
CBi control byte i (i = 1, 2, 3)
TELEFUNKEN Semiconductors
Rev. A1, 21-Aug-96
Preliminary Information
5 (14)

5 Page





U2733B-C arduino
U2733B-C
Phase Noise Performance
(Example:
SFeff = 16899, SFref,eff = 1120,
fref = 17.92 MHz, IPD = 200 A, reference oscillator:
MARCONI INSTRUMENTS signal generator 2042,
spectrum analysis: HP70000, above shown application
circuit, band A oscillator of U2309B)
10.00 dB/DIV
10.00 dB/DIV
–70.5 dBc/Hz
CENTER 270.384 MHz
RB 100 Hz VB 100 Hz
Figure 7.
SPAN 10.00 kHz
ST 3.050 sec
12481
CENTER 270.384 MHz
RB 1.00 kHz VB 1.00 kHz
Figure 8.
SPAN 200.0 kHz
ST 600.0 msec
12482
TELEFUNKEN Semiconductors
Rev. A1, 21-Aug-96
Preliminary Information
11 (14)

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