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PDF IDT72V3663 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V3663 | |
| Descripción | (IDT72V36x3) 3.3 VOLT CMOS SyncFIFOTM | |
| Fabricantes | IDT | |
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3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36
4,096 x 36
8,192 x 36
IDT72V3653
IDT72V3663
IDT72V3673
FEATURES
• Memory storage capacity:
IDT72V3653 – 2,048 x 36
IDT72V3663 – 4,096 x 36
IDT72V3673 – 8,192 x 36
• Clock frequencies up to 100 MHz (6.5 ns access time)
• Clocked FIFO buffering data from Port A to Port B
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Big- or Little-Endian format for word and byte bus sizes
• Retransmit Capability
• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible versions of the 5V operating
IDT723653/723663/723673
• Pin compatible with the lower density parts, IDT72V3623/
72V3633/72V3643
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RS1
RS2
PRS
RT
RTM
FIFO1
Mail1,
Mail2,
Reset
Logic
36
FIFO
Retransmit
Logic
A0-A35
Mail 1
Register
36
RAM ARRAY
2,048 x 36
36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
MBF1
36
B0-B35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
FS2
FS0/SD
FS1/SEN
36
Programmable Flag
Timing
Offset Registers
Mode
13
MBF2
Mail 2
Register
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
36
Port-B
Control
Logic
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4662 drw01
NOVEMBER 2003
DSC-4662/2
1 page  
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
MBA
MBB
Name
Port A Mailbox
Select
Port B Mailbox
Select
MBF1
Mail1 Register Flag
MBF2
Mail2 Register Flag
RS1, RS2 Resets
PRS/ PartialReset/
RT Retransmit
RTM
SIZE(1)
W/RA
W/RB
Retransmit Mode
Bus Size Select
(Port B)
Port A Write/
Read Select
Port B Write/
Read Select
I/O Description
I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and
a LOW level selects FIFO data for output.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH
following either a Reset (RS1) or Partial Reset (PRS).
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH
following either a Reset (RS2) or Partial Reset (PRS).
I A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
setsthePortBoutputregistertoallzeroes. ALOW-to-HIGHtransition on RS1 selects the programming
method (serial or parallel) and one of five programmable flag default offsets. It also configures Port
B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RS1 is LOW.
I ThispinmuxedforbothPartialResetandRetransmitoperations,itisusedinconjunctionwiththeRTM
pin. If RTM is LOW, then a LOW on this pin initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently
selectedbussize,endian arrangement,programmingmethod(serialorparallel),andprogrammable
flag settings are all retained. If RTM is HIGH, then a LOW on this pin performs a Retransmit and initializes
the read pointer only, to the first memory location.
I This pin is used in conjunction with the RT pin. When RTM is HIGH a Retransmit is performed when
RT is taken HIGH.
I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size
and endian arrangement for Port B. The level of SIZE must be static throughout device operation.
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
NOTE:
1. FS2, BM and Size inputs are not TTL compatible. These inputs should be tied to GND or VCC.
5
5 Page 
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
TABLE 1 — FLAG PROGRAMMING
FS2
FS1/SEN
FS0/SD
RS1
X AND Y REGlSTERS(1)
H H H↑
H H L↑
H L H↑
L H H↑
L L H↑
L H L↑
H L L↑
L L L↑
64
16
8
256
1,024
Serial programming via SD
Parallel programming via Port A(2,4)
IP Mode(3,4)
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
2. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
3. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
4. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
— PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers
with one of the five preset values listed in Table 1, the flag select inputs must be
HIGH or LOW during a reset. For example, to load the preset value of 64 into
X and Y, FS0, FS1 and FS2 must be HIGH when RS1 returns HIGH. For
the relevant preset value loading timing diagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
To program the X and Y registers from Port A, perform a Reset with FS2
HIGH or LOW and FS0 and FS1 LOW during the LOW-to-HIGH transition of
RS1. The state of FS2 at this point of reset will determine whether the parallel
programming method has Intersp
arity or Non-Interspersed Parity. Refer to Table 1 for Flag Programming
Flag Offset setup. It is important to note that once parallel programming has been
selected during a Master Reset by holding both FS0 & FS1 LOW, these inputs
must remain LOW during all subsequent FIFO operation. They can only be
toggled HIGH when future Master Resets are performed and other program-
ming methods are desired.
After this reset is complete, the first two writes to the FIFO do not store data
inRAM. ThefirsttwowritecyclesloadtheoffsetregistersintheorderY,X. On
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timing diagram. For Non-Interspersed Parity mode the Port A data inputs used
by the Offset registers are (A10-A0), (A11-A0), or (A12-A0) for the IDT72V3653,
IDT72V3663, or IDT72V3673, respectively. For Interspersed Parity mode the
Port A data inputs used by the Offset registers are (A11-A9, A7-A0), (A12-A9,
A7-A0), or (A13-A9, A7-A0) for the IDT72V3653, IDT72V3663, or IDT72V3673,
respectively. Thehighestnumberedinputisusedasthemostsignificantbitof
the binary number in each case. Valid programming values for the registers
range from 1 to 2,044 for the IDT72V3653; 1 to 4,092 for the IDT72V3663; and
1 to 8,188 for the IDT72V3673. After all the offset registers are programmed
from Port A, the FIFO begins normal operation.
INTERSPERSED PARITY
Interspersed Parity is selected during a Master Reset of the FIFO. Refer
to Table 1 for the set-up configuration of Interspersed Parity. The Interspersed
Parity function allows the user to select the location of the parity bits in the word
loaded into the parallel port (A0-An) during programming of the flag offset
values. If Interspersed Parity is selected then during parallel programming of
the flag offset values, the device will ignore data line A8. If Non-Interspersed
Parity is selected then data line A8 will become a valid bit. If Interspersed Parity
is selected serial programming of the offset values is not permitted, only parallel
programming can be done.
— SERIAL LOAD
To program the X and Y registers serially, initiate a Reset with FS2 LOW,
FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH transition of RS1.
After this reset is complete, the X and Y register values are loaded bit-wise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the
FS1/SEN input is LOW. There are 22-, 24- or 26-bit writes needed to complete
the programming for the IDT72V3653, IDT72V3663 or the IDT72V3673,
respectively. ThetworegistersarewrittenintheorderY,X. Eachregistervalue
can be programmed from 1 to 2,044 (IDT72V3653), 1 to 4,092 (IDT72V3663)
or 1 to 8,188 (IDT72V3673).
When the option to program the offset registers serially is chosen, the Full/
Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/
IR is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
See Figure 6, Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
(CSA)andPortAWrite/Readselect(W/RA). TheA0-A35linesareintheHigh-
impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW,andFF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent
of any concurrent reads on Port B.
The Port B control signals are identical to those of Port A with the exception
that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read
select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35
lines are in the high-impedance state when either CSB is HIGH or W/RB is
LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RB is
HIGH.
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT72V3663.PDF ] | |
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