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PDF IDT7035L Data sheet ( Hoja de datos )

Número de pieza IDT7035L
Descripción HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM
Fabricantes IDT 
Logotipo IDT Logotipo



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No Preview Available ! IDT7035L Hoja de datos, Descripción, Manual

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HIGH-SPEED
8K x 18 DUAL-PORT
STATIC RAM
IDT7035S/L
Features
x True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x High-speed access
– Commercial: 15/20ns (max.)
x Low-power operation
– IDT7035S
Active: 800mW (typ.)
Standby: 5mW (typ.)
– IDT7035L
Active: 800mW (typ.)
Standby: 1mW (typ.)
x Separate upper-byte and lower-byte control for multiplexed
bus compatibility
x IDT7035 easily expands data bus width to 36 bits or more
using the Master/Slave select when cascading more than
one device
x M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
x Interrupt Flag
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x Battery backup operation—2V data retention
x TTL-compatible, single 5V (±10%) power supply
x Available in 100-pin Thin Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O9L-I/O17L
I/O0L-I/O8L
BUSYL(1,2)
I/O
Control
I/O
Control
A12L
A0L
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
13
SEML
INTL(2)
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
M/S
Address
Decoder
CER
OER
R/WR
I/O9R-I/O17R
I/O0R-I/O8R
BUSYR(1,2)
A12R
A0R
SEMR
INTR(2)
4088 drw 01
©1999 Integrated Device Technology, Inc.
SEPTEMBER 1999
1
DSC 4088/5

1 page




IDT7035L pdf
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7035S
7035L
Symbol
Parameter
Test Conditions
Min. Max. Min. Max. Unit
|ILI| Input Leakage Current(1)
VCC = 5.5V, VIN = 0V to VCC
___ 10 ___
5 µA
|ILO| Output Leakage Current
CE = VIH, VOUT = 0V to VCC
___ 10 ___
5 µA
VOL Output Low Voltage
IOL = 4mA
___ 0.4 ___ 0.4 V
VOH Output High Voltage
IOH = -4mA
2.4 ___ 2.4 ___ V
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
4088 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
Symbol
Parameter
Test Condition
Version
7035X15
Com'l Only
Typ.(2) Max.
7035X20
Com'l Only
Typ.(2) Max.
Unit
ICC Dynamic Operating Current CE = VIL, Outputs Open
(Both Ports Active)
SEM = VIH
f = fMAX(3)
COM'L
IND
S 170 310 160 290 mA
L 170 260 160 240
S ____ ____ 160 370
L ____ ____ 160 320
ISB1 Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM'L S 20 60 20 60 mA
L 20 50 20 50
IND S ____ ____ 20 90
L ____ ____ 20 70
ISB2 Standby Current
CE"A" = VIL and CE"B" = VIH(5)
(One Port - TTL Level Inputs) Active Port Outputs Open,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
IND
S 105 190 95 180 mA
L 105 160 95 150
S ____ ____ 95 240
L ____ ____ 95 210
ISB3 Full Standby Current (Both Both Ports CEL and
Ports - All CMOS Level
CER > VCC - 0.2V
Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L S 1.0 15 1.0 15 mA
L 0.2 5 0.2 5
IND S ____ ____ 1.0 30
L ____ ____ 0.2 10
ISB4 Full Standby Current
CE"A" < 0.2V and
(One Port - All CMOS Level CE"B" > VCC - 0.2V(5)
Inputs)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open
f = fMAX(3)
COM'L
IND
S 100 170 90 155 mA
L 100 140 90 130
S ____ ____ 90 225
L ____ ____ 90 200
NOTES:
4088 tbl 09
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 120mA (TYP)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.542

5 Page





IDT7035L arduino
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
7035X15
Com'l Only
7035X20
Com'l Only
Symbol
BUSY TIMING (M/S=VIH)
Parameter
Min. Max. Min. Max. Unit
tBAA BUSY Access Time from Address Match
____ 15 ____ 20 ns
tBDA BUSY Disable Time from Address Not Matched
____ 15 ____ 20 ns
tBAC BUSY Acce ss Time from Chip Enable Low
____ 15 ____ 20 ns
tBDC BUSY Acce ss Time from Chip Enable High
tAPS Arbitration Priority Set-up Time(2)
____ 15 ____ 17 ns
5 ____ 5 ____ ns
tBDD BUSY Disable to Valid Data(3)
____ 18 ____ 30 ns
tWH Write Hold After BUSY(5)
BUSY TIMING (M/S=VIL)
12 ____ 15 ____ ns
tWB BUSY Input to Write(4)
0 ____ 0 ____ ns
tWH Write Hold After BUSY(5)
12 ____ 15 ____ ns
PORT-TO-PORT DELAY TIMING
tWDD Write Pulse to Data Delay(1)
____ 30 ____ 45 ns
tDDD Write Data Valid to Read Data Delay(1)
____ 25 ____ 30 ns
NOTES:
4088 tbl 14
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write with
Port-To-Port Delay (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
61.412

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