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Número de pieza | DM9000A | |
Descripción | Ethernet Controller | |
Fabricantes | Davicom | |
Logotipo | ||
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DM9000A
Ethernet Controller with General Processor Interface
DAVICOM Semiconductor, Inc.
DM9000A
Ethernet Controller
with General Processor Interface
DATA SHEET
Preliminary
Version: DM9000A-DS-P03
Apr. 21, 2005
Preliminary
Version: DM9000A-DS-P03
Apr. 21, 2005
1
1 page DM9000A
Ethernet Controller with General Processor Interface
10.1.1 Operating Conditions………………………………………………………………………………..………..…45
10.2 DC Electrical Characteristics (VDD = 3.3V)……………………………….…………………………..…………45
10.3 AC Electrical Characteristics & Timing Waveform……………………………………………………..…..……46
10.3.1 TP Interface…………………………………………………………………………………………..…………46
10.3.2 Oscillator/Crystal Timing……………………………………………………………………………….………46
10.3.3 Processor Register Read Timing…………………………………………………………………….….………46
10.3.4 Processor Register Write Timing………………………………………………………………….…….………47
10.3.5 EEPROM Interface Timing………………………………………………………………………….……..……48
11. Application Notes………………………………………………………………………………….……………49
11.1 Network Interface Signal Routing………………………………………………………………….………………49
11.2 10Base-T/100Base-TX (Auto MDIX Application)…….…………………………………………….….…………49
11.3 10Base-T/100Base-TX (Non Auto MDIX Application)…………………………………………….…..…………50
11.4 Power Decoupling Capacitors…………………………………………………………..…………….……………51
11.5 Ground Plane Layout………………………………………………………………………………….……………52
11.6 Power Plane Partitioning……………………………………………………………………………………………53
11.7 Magnetics Selection Guide………………………………………………………………………………….………54
11.8 Crystal Selection Guide…………………………………………………………………………..…………………54
12. Package Information………………………………………………………………………….……………..55
13. Ordering Information………………………………………………………………………….……….……56
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
5
5 Page 28,29,31 GP3,GP2,GP1
DM9000A
Ethernet Controller with General Processor Interface
General I/O Ports
I/O Registers GPCR and GPR can program these pins
These pins are input ports at default.
5.2 EEPROM Interface
Pin No.
Pin Name
19 EEDIO
20 EECK
21 EECS
5.3 Clock Interface
Pin No.
Pin Name
43 X2
44 X1
Type
Description
I/O,PD IO Data to EEPROM
O,PD
O,PD
Clock to EEPROM
This pin is also used as the strap pin of the polarity of the INT pin
When this pin is pulled high, the INT pin is low active; otherwise the INT pin is
high active
Chip Select to EEPROM
This pin is also used as a strap pin to define the internal memory data
bus width. When it is pulled high, the memory access bus is 8-bit;
Otherwise it is 16-bit.
Type
O
I
Crystal 25MHz Out
Crystal 25MHz In
Description
5.4 LED Interface
Pin No.
Pin Name
39 LED1
38 LED2
Type
O
O
Description
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY.
This pin also acts as ISA bus IO16 defined in EEPROM setting in 16-bit
mode.
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
This pin also acts as ISA bus IOWAIT or WAKE defined in EEPROM
setting in 16-bit mode.
5.5 10/100 PHY/Fiber
Pin No.
Pin Name
46 SD
48 BGGND
1 BGRES
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
Type
I
P
I/O
Description
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Bandgap Ground
Bandgap Pin
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet DM9000A.PDF ] |
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