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PDF WSF512K32-XXX Data sheet ( Hoja de datos )
| Número de pieza | WSF512K32-XXX | |
| Descripción | 512KX32 SRAM / FLASH MODULE | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
WSF512K32-XXX
512KX32 SRAM / FLASH MODULE
FEATURES
Access Times of 25ns (SRAM) and 70, 90ns
(FLASH)
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight - 13 grams typical
Packaging
• 66 pin, PGA Type, 1.385" square HIP, Hermetic
Ceramic HIP (Package 402)
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880")
square (Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (Figure 2). Package to be developed.
FLASH MEMORY FEATURES
100,000 Erase/Program Cycles
Sector Architecture
• 8 equal size sectors of 64KBytes each
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
512Kx32 SRAM
5 Volt Programming; 5V ± 10% Supply
512Kx32 5V Flash
Embedded Erase and Program Algorithms
Organized as 512Kx32 of SRAM and 512Kx32 of
Flash Memory with common Data Bus
Low Power CMOS
Commercial, Industrial and Military Temperature
Ranges
Hardware Write Protection
Page Program Operation and Internal Program
Control Time.
* This product is subject to change without notice.
Note: Programming information available upon request.
TTL Compatible Inputs and Outputs
Figure 1 – PIN CONFIGURATION FOR WSF512K32-29H2X
Top View
1 12 23
I/O8 FWE2# I/O15
I/O9 SWE2# I/O14
I/O10 GND
I/O13
A14 I/O11 I/O12
A16 A10
OE#
A11 A9
A17
34 45 56
I/O24
VCC I/O31
I/O25 SWE4# I/O30
I/O26 FWE4# I/O29
A7 I/O27 I/O28
A12 A4 A1
SWE1# A5 A2
Pin Description
I/O0-31
A0-18
SWE1-4#
SCS#
OE#
VCC
GND
NC
FWE1-4#
FCS#
Data Inputs/Outputs
Address Inputs
SRAM Write Enables
SRAM Chip Select
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enables
Flash Chip Select
A0 A15 FWE1#
A18 VCC I/O7
I/O0 FCS# I/O6
I/O1 SCS# I/O5
I/O2 I/O3
I/O4
11 22
33
A13 A6 A3
A8 FWE3# I/O23
I/O16 SWE3# I/O22
I/O17
GND I/O21
I/O18
I/O19
I/O20
44 55 66
OE#
A0-18
SCS#
FCS#
FWE1# SWE1#
Block Diagram
FWE2# SWE2#
FWE3# SWE3#
FWE4# SWE4#
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
I/O0-7
I/O8-15
I/O16-23
I/O24-31
May 2006
Rev. 9
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
WSF512K32-XXX
FIGURE 4 – SRAM TIMING WAVEFORM - READ CYCLE
ADDRESS
DATA I/O
tRC
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE 1, (SCS# = OE# = VIL, SWE# = FCS# = VIH)
ADDRESS
SCS#
SOE#
DATA I/O
tRC
tAA
tACS
tCLZ
tCHZ
tOE
tOLZ
HIGH IMPEDANCE
tOHZ
DATA VALID
READ CYCLE 2, (SWE# = FCS# = VIH)
FIGURE 5 – SRAM WRITE CYCLE - SWE# CONTROLLED
ADDRESS
SCS#
SWE#
DATA I/O
tWC
tAW
tCW
tAH
tAS tWP
tWHZ
tOW
tDW tDH
DATA VALID
WRITE CYCLE 1, SWE# CONTROLLED (FCS# = VIH)
FIGURE 6 – SRAM WRITE CYCLE - SCS# CONTROLLED
May 2006
Rev. 9
ADDRESS
SCS#
tAS
tWC
tAW
tCW
tAH
SWE#
DATA I/O
tWP
tDW tDH
DATA VALID
WRITE CYCLE 2, SCS# CONTROLLED (FCS# = VIH)
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
WSF512K32-XXX
FIGURE 10 AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM
OPERATIONS FOR FLASH MEMORY
FCS#
tCH
OE#
FWE#
tOEH
D7
D0-D6
D7
tDF
tOE
tCE
tWHWH 1 or 2
D7#
D0-D6 = Invalid
tWHWH 1 or 2
D7
tOH
D7 =
Valid Data
D0-D7
Valid Data
tOE
D7
Valid Data
High Z
High Z
Note: SCS# = VIH
May 2006
Rev. 9
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
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| PDF Descargar | [ Datasheet WSF512K32-XXX.PDF ] | |
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