PDF WSF41632-22XX Data sheet ( Hoja de datos )

Número de pieza	WSF41632-22XX
Descripción	128KX32 SRAM & 512Kx32 FLASH MIXED MODULE
Fabricantes	White Electronic
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No Preview Available ! www.DataSheet4U.com White Electronic Designs WSF41632-22XX PRELIMINARY* 128KX32 SRAM & 512Kx32 FLASH MIXED MODULE FEATURES Access times of 25ns (SRAM) and 120ns (FLASH) Packaging Built-in decoupling caps and multiple ground pins for low noise operation Weight - 13 grams typical • 66 pin, PGA Type, 1.385" square HIP, hermetic ceramic HIP (Package 402) • 68 lead, hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height Designed to ﬁt JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 2). Package to be developed. 128Kx32 SRAM FLASH MEMORY FEATURES 100,000 erase/program cycles minimum Sector architecture • 8 equal size sectors of 64KBytes each • Any combination of sectors can be concurrently erased. Also supports full chip erase 512Kx32 5V Flash 5V programming; 5V ± 10% supply Organized as 128Kx32 of SRAM and 512Kx32 of Flash Memory with common data bus Low power CMOS Commercial, industrial and military temperature ranges Embedded erase and program algorithms Hardware write protection Page program operation and internal program control time. Note: For programming information refer to ﬂash programming 4M5 application note. TTL compatible inputs and outputs * This product is under development, is not qualiﬁed or characterized and is subject to change without notice. PIN CONFIGURATION FOR WSF41632-22H2X Top View 1 12 23 I/O8 FWE2# I/O15 34 45 56 I/O24 VCC I/O31 I/O9 SWE2# I/O14 I/O25 SWE4# I/O30 I/O10 GND I/O13 I/O26 FWE4# I/O29 A14 I/O11 I/O12 A7 I/O27 I/O28 A16 A10 OE# A12 A4 A1 Pin Description D0-31 Data Inputs/Outputs A0-18 Address Inputs SWE#1-4 SRAM Write Enables SCS# SRAM Chip Select OE# Output Enable VCC Power Supply GND Ground NC Not Connected FWE#1-4 Flash Write Enables FCS Flash Chip Select A11 A9 A17 A0 A15 FWE1# A18 VCC I/O7 I/O0 FCS# I/O6 I/O1 SCS# I/O5 SWE1# A5 A13 A6 A8 FWE3# I/O16 SWE3# I/O17 GND A2 A3 I/O23 I/O22 I/O21 Block Diagram OE# A0-18 SCS# FCS# FWE1# SWE1# FWE2# SWE2# FWE3# SWE3# FWE4# SWE4# 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 11 22 33 44 55 66 I/O0-7 I/O8-15 I/O16-23 I/O24-31 White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. October, 2002 Rev. 4 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 3 – SRAM TIMING WAVEFORM - READ CYCLE ADDRESS DATA I/O tRC tAA tOH PREVIOUS DATA VALID DATA VALID READ CYCLE 1, (SCS# = OE# = VIL, SWE# = FCS# = VIH) ADDRESS SCS# SOE# DATA I/O tRC tAA tACS tCLZ tCHZ tOE tOLZ HIGH IMPEDANCE tOHZ DATA VALID READ CYCLE 2, (SWE# = FCS# = VIH) FIGURE 4 – SRAM WRITE CYCLE - SWE# CONTROLLED ADDRESS SCS# SWE# DATA I/O tWC tAW tCW tAH tAS tWP tWHZ tOW tDW tDH DATA VALID WRITE CYCLE 1, SWE# CONTROLLED (FCS# = VIH) FIGURE 5 – SRAM WRITE CYCLE - SCS# CONTROLLED ADDRESS SCS# tAS tWC tAW tCW tAH SWE# DATA I/O tWP tDW tDH DATA VALID WRITE CYCLE 2, SCS# CONTROLLED (FCS# = VIH) White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. October, 2002 Rev. 4 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs WSF41632-22XX PRELIMINARY FIGURE 9 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY FCS# tCH OE# FWE# tOEH D7 D0-D6 D7 tDF tOE tCE tWHWH 1 or 2 D7# D0-D6 = Invalid tWHWH 1 or 2 D7 tOH D7 = Valid Data D0-D7 Valid Data tOE D7 Valid Data High Z High Z Note: SCS# = VIH White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. October, 2002 Rev. 4 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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