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PDF WF4M32-XXX5 Data sheet ( Hoja de datos )
| Número de pieza | WF4M32-XXX5 | |
| Descripción | 4Mx32 5V FLASH MODULE | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
WF4M32-XXX5
PRELIMINARY*
4Mx32 5V FLASH MODULE
FEATURES
Access Times of 100, 120, 150ns
Packaging:
• 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
• 68 lead, 40mm Low Profile CQFP (Package
502), 3.5mm (0.140") height.
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880")
square (Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990CQFJ
footprint (Fig. 3)
Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8
chip
• Any combination of sectors can be erased. Also
supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 4Mx32
User configurable as 2x4Mx16 or 4x4Mx8 in HIP
and G4T packages.
Commercial, Industrial, and Military Temperature
Ranges
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
RESET# pin resets internal state machine to the
read mode.
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation, Separate Power and
Ground Planes to improve noise immunity
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
FIGURE 1 – PIN CONFIGURATION FOR WF4M32-XH2X5
Top View
1 12 23
I/O8 RESET# I/O15
34 45 56
I/O24
VCC I/O31
I/O9
CS2#
I/O14
I/O25
CS4#
I/O30
I/O10 GND
I/O13
I/O26
NC I/O29
A14 I/O11 I/O12
A7 I/O27
I/O28
A16 A10
OE#
A12 A4
A1
A11 A9
A17
A21 A5
A2
A0 A15 WE#
A18 VCC I/O7
I/O0
CS1#
I/O6
A13
A8
I/O16
A6
A20
CS3#
A3
I/O23
I/O22
I/O1 A19
I/O5
I/O17 GND I/O21
I/O2 I/O3
I/O4
11 22
33
I/O18
I/O19
I/O20
44 55 66
PIN DESCRIPTION
I/O0-31
A0-21
WE#
CS1-4#
OE#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
VCC
VSS
RESET#
Power Supply
Ground
Reset
Block Diagram
CS1#
CS2#
CS3#
CS4#
A21
OE#
WE#
A0-20
RESET#
2M x 8
2M x 8
2M x 8
2M x 8
2Mx 8
2M x 8
2M x 8
2M x 8
I/O0-7
I/O8-15
I/O16-23
I/O24-31
June 2004
Rev. 6
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
WF4M32-XXX5
PRELIMINARY
AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS,
CS# CONTROLLED
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-100
Min Max
-120
Min Max
-150
Min Max
Unit
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
tAVAV tWC 100 120 150
ns
tWLEL
tWS
0
0
0 ns
tELEH
tCP
45
50
50
ns
tAVEL
tAS
0
0
0 ns
tDVEH
tDS
45
50
50
ns
tEHDX
tDH
0
0
0 ns
tELAX
tAH
45
50
50
ns
tEHEL
tCPH
20
20
20
ns
tWHWH1
300 300 300 µs
tWHWH2
15 15 15 sec
tGHEL
0
0
0 µs
44 44 44 sec
Chip Erase Time (3)
256 256 256 sec
Output Enable Hold Time (4)
tOEH 10 10 10 ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
June 2004
Rev. 6
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
WF4M32-XXX5
PRELIMINARY
FIGURE 9 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED
ALGORITHM OPERATIONS
June 2004
Rev. 6
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
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