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PDF WED2DL32512V Data sheet ( Hoja de datos )

Número de pieza WED2DL32512V
Descripción 512Kx32 Synchronous Pipeline Burst SRAM
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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WED2DL32512V
512Kx32 Synchronous Pipeline Burst SRAM PRELIMINARY*
FEATURES
s Fast clock speed: 200, 166, 150 & 133MHz
s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
s Single +3.3V power supply (VDD)
s Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
s Snooze Mode for reduced-power standby
s Single-cycle deselect
s Common data inputs and data outputs
s Individual Byte Write control and Global Write
s Clock-controlled and registered addresses, data I/Os and control signals
s Burst control (interleaved or linear burst)
s Packaging:
• 119-bump BGA package
s Low capacitive bus loading
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16
SRAMs into a single BGA package to provide 512K x 32 configura-
tion. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE), burst control input (ADSC) and byte write enables (BW0-3).
Asynchronous inputs include the output enable (OE), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. Write cycles
can be from one to four bytes wide, as controlled by the write control
inputs. Burst operation can be initiated with the address status
controller (ADSC) input.
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
FIG. 1
PIN CONFIGURATION
(TOP VIEW)
123 4 5
A VDDQ SA
SA
NC
SA
B NC SA SA ADSC SA
C NC SA SA VDD SA
D DQc NC VSS NC VSS
E DQc DQc VSS CE VSS
F VDDQ DQc VSS OE VSS
G DQc DQc BWc NC BWb
H DQc DQc VSS NC VSS
J VDDQ VDD NC
VDD
NC
K DQd DQd VSS
CLK
VSS
L DQd DQd BWd NC BWa
M VDDQ DQd VSS BWE VSS
N DQd DQd VSS
SA1
VSS
P DQd NC VSS SA0 VSS
R NC SA MODE VDD NC
T NC NC SA SA SA
U VDDQ DC
DC
DC
DC
NOTE: DC = Do Not Connect
6
SA
SA
SA
NC
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
NC
SA
NC
NC
7
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
SA
CLK
ADSC
OE
BWE
CE
MODE
ZZ
BWa
BWb
BLOCK DIAGRAM
512K x 16
SSRAM
DQa
DQb
512K x 16
SSRAM
DQc
DQd
BWc
BWd
January 2000 Rev. 0
1 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

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WED2DL32512V pdf
WED2DL32512V
AC CHARACTERISTICS
Parameter
Clock
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
Output Times
Clock to output valid
Clock to output invalid (2)
Clock to output on Low-Z (2,3,4)
Clock to output in High-Z (2,3,4)
OE to output valid (5)
OE to output in Low-Z (2,3,4)
OE to output in High Z (2,3,4)
Setup Times
Address (6,7)
Address status (ADSC) (6,7)
Write signals (BWa-BWd, BWE) (6,7)
Data-in (6,7)
Chip enables (CE) (6,7)
Hold Times
Address (6,7)
Address status (ADSC) (6,7)
Write Signals (BWa-BWd, BWE) (6,7)
Data-in (6,7)
Chip Enables (CE) (6,7)
Symbol
tKC
tKF
tKH
tKL
tKQ
tKQX
tKQLZ
tKQHZ
tOEQ
tOELZ
tOEHZ
tAS
tADSS
tWS
tDS
tCES
tAH
tADSH
tWH
tDH
tCEH
200MHz
Min Max
5.0
200
2.0
2.0
2.5
1.5
0
3.0
2.5
0
2.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
166MHz
Min Max
6.0
166
2.4
2.4
3.5
1.25
0
3.5
3.5
0
3.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
150MHz
Min Max
6.6
150
2.6
2.6
3.8
1.25
0
3.8
3.8
0
3.8
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
133MHz
Min Max
7.5
133
2.6
2.6
4.0
1.5
0
4.0
4.0
0
4.0
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
Units
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Test conditions as specified with the output loading as shown in Figure 1 for 3.3V 1/0 and Figure 3 for 2.5V 1/0 unless otherwise noted.
2. This parameter is measured with output load as shown in Figure 2 for 3.3V 1/0 and Figure 4 for 2.5V 1/0.
3. This parameter is sampled.
4. Transition is measured ±500mV from steady state voltage.
5. OE is a “Don’t Care” when a byte write enable is sampled LOW.
6. A WRITE cycle is defined by at least one byte write enable LOW for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC
LOW for the required setup and hold times.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADSC is LOW and chip enabled. All other
synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when ADSC is LOW to remain enabled.
OUTPUT LOADS
Output
ZZ00==5050
50
VtV=t 1=.51V.5fVor 3.3V I/O
Vt = 1.25V for 2.5V I/O
AC Output Load Equivalent
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3.3V I/O
2.5V I/O
VSS to 3.0
VSS to 2.5
11
1.5 1.25
1.5 1.25
See figure, at left
Unit
V
ns
V
V
5 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

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