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PDF EDI2AG272128V-D1 Data sheet ( Hoja de datos )

Número de pieza EDI2AG272128V-D1
Descripción 2 Megabyte Sync/Sync Burst
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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No Preview Available ! EDI2AG272128V-D1 Hoja de datos, Descripción, Manual

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White Electronic Designs
EDI2AG272128V-D1
ADVANCED*
2 Megabyte Sync/Sync Burst, Small Outline DIMM
FEATURES
2x128Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear Burst Mode
Clock Controlled Registered Bank Enables (E1#, E2#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables
(BW1# - BW8#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally self-timed Write
Gold Lead Finish
3.3V ± 10% Operation
Access Speed(s): TKHQV=8.5, 9, 10, 12ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access Speed
Single total array Clock
Multiple Vcc and Gnd
The EDI2AG272128VxxD1 is a Synchronous/Synchronous
Burst SRAM, 72 position DIMM (144 contacts) Module,
organized as 2x128Kx72. The Module contains four
(4) Synchronous Burst Ram Devices, packaged in the
industry standard JEDEC 14mmx20mm TQFP placed on
a Multilayer FR4 Substrate. The module architecture is
defined as a Sync/Sync Burst, Flow-Through, with support
for linear burst. This module provides High Performance,
2-1-1-1 accesses when used in Burst Mode, and used as
a Synchronous Only Mode, provides a high performance
cost advantage over BiCMOS aysnchronous device
architectures.
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP#/ADV# High, which provides for
Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in relation
to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well as
an Asynchronous Output enable. This Module has been
defined with full flexibility, which allows individual control
of each of the eight bytes, as well as Quad Words in both
Read and Write Operations.
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




EDI2AG272128V-D1 pdf
White Electronic Designs
EDI2AG272128V-D1
ADVANCED
SYNCHRONOUS BURST - TRUTH TABLE
Operation
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
E1# E2# ADSP# ADSC# ADV# GW# G#
HX
X
L X XX
XH
X
L X XX
LH
L
X XXL
LH
L
X X XH
HL
L
X XXL
HL
L
X X XH
LH
H
L X LX
HL
H
L X LX
LH
H
L XHL
LH
H
L X HH
HL
H
L XHL
HL
H
L X HH
XH
X
H
L HL
XH
X
H
L HH
HX
X
H
L HL
HX
X
H
L HH
HH
X
H
L HL
HH
X
H
L HH
HH
X
H
L HL
HH
X
H
L HH
XH
H
H
L LX
HH
X
H
L LX
HX
H
H
L LX
HH
X
H
L LX
XH
H
H HHL
XH
H
H H HH
HX
H
H HHL
HX
H
H H HH
HH
X
H HHL
HH
X
H H HH
HH
X
H HHL
HH
X
H H HH
XH
H
H H LX
HH
X
H H LX
HX
H
H H LX
HH
X
H H LX
CK DQ Addr. Used
L-H High-Z None
L-H High-Z None
L-H Q
External
L-H High-Z External
L-H Q
External
L-H High-Z External
L-H D
External
L-H D
External
L-H Q
External
L-H High-Z External
L-H Q
External
L-H High-Z External
L-H Q
Next
L-H High-Z
Next
L-H Q
Next
L-H High-Z
Next
L-H Q
Next
L-H High-Z
Next
L-H Q
Next
L-H High-Z
Next
L-H D
Next
L-H D
Next
L-H D
Next
L-H D
Next
L-H Q
Current
L-H High-Z Current
L-H Q
Current
L-H High-Z Current
L-H Q
Current
L-H High-Z Current
L-H Q
Current
L-H High-Z Current
L-H D
Current
L-H D
Current
L-H D
Current
L-H D
Current
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

5 Page





EDI2AG272128V-D1 arduino
White Electronic Designs
EDI2AG272128V-D1
ADVANCED
PACKAGE DESCRIPTION
Package No. 409
144 Lead
Small Outline DIMM
2.667 MAX.
0.157
U1
U3
P1
0.913
1.112
0.181 TYP
1.291
1.490
R18 1.000
MAX.
R17 0.788
0.175
MAX.
ORDERING INFORMATION
Part Number
EDI2AG272128V85D1*
EDI2AG272128V9D1*
EDI2AG272128V10D1
EDI2AG272128V12D1
*Consult Factory for Availability
Organization
4x256Kx72
4x256Kx72
4x256Kx72
4x256Kx72
Voltage
3.3
3.3
3.3
3.3
Speed (ns)
8.5
9
10
12
Package
144 Small Outline DIMM
144 Small Outline DIMM
144 Small Outline DIMM
144 Small Outline DIMM
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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