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PDF IRAUDAMP3 Data sheet ( Hoja de datos )
| Número de pieza | IRAUDAMP3 | |
| Descripción | 120W x 6-Channel Class D Audio Power AMplifier | |
| Fabricantes | International Rectifier | |
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IRAUDAMP3
120W x 6 Channel Class D Audio Power Amplifier
using IRS20124S and IRF6645
By
Jun Honda, Johan Strydom and Jorge Cerezo
Table of Contents
Page
Introduction .......................................................................................... 1
Specifications ....................................................................................... 2
Functional Description.......................................................................... 4
Protection .............................................................................................11
Typical Performance ............................................................................15
Design Documents ..............................................................................20
The IRAUDAMP3 reference design is an example of a complete six-channel 120W half-bridge
Class D audio power amplifier. The reference design is intended to demonstrate how to use the
IRS20124S, implement protection circuits, and design an optimum PCB layout using IRF6645
DirectFET® MOSFETs. The modular design consists of a motherboard with three identical daughter
boards. The resulting design requires no heat-sinking for normal operation. The reference design
includes all the required housekeeping power supplies for ease of use.
www.irf.com
1 page  
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Power-on Procedure
1. Apply ±35V at the same time
2. Apply audio signal
Note: Improper power on procedure could result start up failure.
Power-off Procedure
1. Remove audio input signal
2. Turn off ±35V at the same time
Functional Description
Class D operation
Referring to CH-1 as an example, the op-amp U1 forms a front-end second-order
integrator with C1 & C2. This integrator receives a rectangular waveform from the Class
D switching stage and outputs a quadratic oscillatory waveform as a carrier signal. To
create the modulated PWM, the input signal shifts the average value of this quadratic
waveform (through gain relationship between R28 and R9 + R1) so that the duty varies
according to the instantaneous value of the analog input signal. The signal is then
quantized by the threshold of the CMOS inverter U2. The transistor Q1 level-shifts the
PWM signal down to the IRS20124S gate-driver (referenced to –B) which internally splits
this signal into two signals, with opposite polarity and added deadtime, for high-side and
low-side MOSFET gate signals respectively.
The IRS20124S drives two IRF6645 DirectFET MOSFETs in the power-stage to provide
the amplified digital PWM waveform. The amplified analog output is re-created by
demodulating the amplified PWM. This is done by means of the LC low-pass filter (LPF)
formed by L1 and C18, which filters out the Class D switching carrier signal.
Feedback
U1 U2
Daughter board +B
Σ
Integrator
Comparator
U1
GND
Q1
Level
Shifter
IRS20124S
Gate
Driver
LPF
IRF6645
-B
Simplified block diagram of Class D amplifier
www.irf.com
4
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Selectable Deadtime
The DT/SD pin provides two functions: 1) setting deadtime and 2) selecting shutdown.
The IRS20124S determines its operation mode based on the voltage applied to the
DT/SD pin. An internal comparator translates which mode is being used by comparing
internal reference voltages. Threshold voltages for each mode are set internally by a
resistive voltage divider off VCC, negating the need for a precise, absolute voltage to set
the mode.
1) Threshold voltages for the mode selection are set internally, based on different ratios
of VCC as indicated in the diagram below. In order to avoid drift from the input bias
current of the DT/SD pin, a bias current of greater than 0.5mA is suggested for the
external resistor divider circuit. Suggested values of resistance that are used to set a
deadtime are given below. Resistors with up to 5% tolerance can be used.
Deadtime / operation mode settings vs VDT/SD voltage
Dead-time mode
DT1
DT2
DT3
DT4
Dead-time
~15ns
~25ns
~35ns
~45ns
R1
<10kΩ
3.3kΩ
5.6kΩ
8.2kΩ
R2
open
8.2kΩ
4.7kΩ
3.3kΩ
DT/SD voltage
1.0 x VCC
0.71 x VCC
0.46 x VCC
0.29 x VCC
Default
2) In Shutdown mode, both MOSFETs are turned off simultaneously to stop operation
and protect the circuit during fault conditions. If the DT/SD pin detects an input voltage
below the threshold, 0.23 x VCC, the IRS20124S will output 0V at both HO and LO
outputs, forcing the switching output node to go into a high impedance state.
www.irf.com
10
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet IRAUDAMP3.PDF ] | |
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