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PDF UPD44325082 Data sheet ( Hoja de datos )

Número de pieza UPD44325082
Descripción (UPD44325xx2) 36M-BIT QDRII SRAM 2-WORD BURST OPERATION
Fabricantes NEC 
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44325082, 44325092, 44325182, 44325362
36M-BIT QDRTMII SRAM
2-WORD BURST OPERATION
Description
The µPD44325082 is a 4,194,304-word by 8-bit, the µPD44325092 is a 4,194,304-word by 9-bit, the µPD44325182 is a
2,097,152-word by 18-bit and the µPD44325362 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD44325082, µPD44325092, µPD44325182 and µPD44325362 integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive
edge of K and /K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC FBGA.
Features
1.8 ± 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Two-tick burst for low DDR transaction size
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with µs restart
User programmable impedance output
Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16783EJ1V0DS00 (1st edition)
Date Published October 2004 NS CP(K)
Printed in Japan
The mark shows major revised points.
2003

1 page




UPD44325082 pdf
µPD44325082, 44325092, 44325182, 44325362
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[µPD44325182F5-EQ2]
1 2 3 4 5 6 7 8 9 10 11
A /CQ
VSS
A
/W /BW1 /K NC /R
A VSS CQ
B NC Q9 D9 A NC K /BW0 A NC NC Q8
C NC
NC D10 VSS
A
A
A VSS NC Q7 D8
D NC D11 Q10 VSS VSS
VSS
VSS
VSS
NC
NC
D7
E NC
NC
Q11
VDDQ
VSS
VSS
VSS VDDQ NC
D6
Q6
F NC
Q12
D12 VDDQ
VDD
VSS
VDD VDDQ NC
NC
Q5
G NC
D13
Q13 VDDQ
VDD
VSS
VDD VDDQ NC
NC
D5
H /DLL
VREF
VDDQ VDDQ
VDD
VSS
VDD
VDDQ VDDQ
VREF
ZQ
J NC
NC
D14
VDDQ
VDD
VSS
VDD VDDQ NC
Q4
D4
K NC
NC
Q14
VDDQ
VDD
VSS
VDD VDDQ NC
D3
Q3
L NC
Q15
D15 VDDQ
VSS
VSS
VSS VDDQ NC
NC
Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC
D17 Q16
VSS
A
A
A VSS NC NC D1
P NC
NC Q17
A
A
C
A
A NC D0 Q0
R TDO TCK
A
A
A /C
A
A
A TMS TDI
A
D0 to D17
Q0 to Q17
/R
/W
/BW0, /BW1
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1. Refer to Package Drawing for the index mark.
2. 2A and 10A are expansion addresses: 10A for 72Mb and 2A for 144Mb.
Preliminary Data Sheet M16783EJ1V0DS
5

5 Page





UPD44325082 arduino
µPD44325082, 44325092, 44325182, 44325362
Byte Write Operation
[µPD44325082]
Operation
Write D0 to D7
Write D0 to D3
Write D4 to D7
Write nothing
K
LH
LH
LH
LH
/K
LH
LH
LH
LH
/NW0
0
0
0
0
1
1
1
1
/NW1
0
0
1
1
0
0
1
1
Remarks 1. H : High level, L : Low level, : rising edge.
2. Assumes a WRITE cycle was initiated. /NW0 and /NW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[µPD44325092]
Operation
Write D0 to D8
Write nothing
K
LH
LH
/K
LH
LH
/BW0
0
0
1
1
Remarks 1. H : High level, L : Low level, : rising edge.
2. Assumes a WRITE cycle was initiated. /BW0 can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[µPD44325182]
Operation
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
K
LH
LH
LH
LH
/K
LH
LH
LH
LH
/BW0
0
0
0
0
1
1
1
1
/BW1
0
0
1
1
0
0
1
1
Remarks 1. H : High level, L : Low level, : rising edge.
2. Assumes a WRITE cycle was initiated. /BW0 and /BW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Preliminary Data Sheet M16783EJ1V0DS
11

11 Page







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