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PDF DP83251 Data sheet ( Hoja de datos )

Número de pieza DP83251
Descripción (DP83251 / DP83255) PLAYER Device
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! DP83251 Hoja de datos, Descripción, Manual

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February 1991
DP83251 55 PLAYERTM Device
(FDDI Physical Layer Controller)
General Description
The DP83251 DP83255 PLAYER device implements one
Physical Layer (PHY) entity as defined by the Fiber Distribut-
ed Data Interface (FDDI) ANSI X3T9 5 Standard The PLAY-
ER device contains NRZ NRZI and 4B 5B encoders and
decoders serializer deserializer framing logic elasticity
buffer line state detector generator link error detector re-
peat filter smoother and configuration switch
Features
Y Low power CMOS-BIPOLAR process
Y Single 5V supply
Y Full duplex operation
Y Separate management interface (Control Bus)
Y Parity on PHY-MAC Interface and Control Bus Interface
Y On-chip configuration switch
Y Internal and external loopback
Y DP83251 for single attach stations
Y DP83255 for dual attach stations
FIGURE 1-1 FDDI Chip Set Block Diagram
TL F 10386 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
BSITM BMACTM PLAYERTM CDDTM and CRDTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10386
RRD-B30M105 Printed in U S A

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DP83251 pdf
2 0 Architecture Description
(Continued)
PHY Port Interface
The PHY Port Interface connects the PLAYER device to
one or more BMAC devices and or PLAYER devices Each
PHY Port Interface consists of two byte-wide-interfaces
one for PHY Request data input to the PLAYER device and
one for the PHY Indicate data output of the PLAYER device
Each byte-wide interface consists of a parity bit (odd parity)
a control bit and two 4-bit symbols
The DP8355 PLAYER device has two PHY Port Interfaces
and the DP83251 has only one PHY Port Interface
Control Bus Interface
The Control Bus Interface connects the PLAYER device to
a wide variety of microprocessors and microcontrollers The
Control Bus is an asynchronous interface which provides
access to 32 8-bit registers
Clock Interface
The Clock Interface consists of 12 5 MHz and 125 MHz
clocks used by the PLAYER device
The clocks are generated by either the Clock Distribution
Device (CDD device) or the Clock Recovery Device (CRD
device)
Miscellaneous Interface
The Miscellaneous Interface consists of
 A reset signal
 User definable sense signals
 User definable enable signals
 Synchronization for cascaded PLAYER devices (a high-
performance non-FDDI mode)
 CMOS power and ground and ECL ground and power
3 0 Functional Description
The PLAYER Device is comprised of four blocks Receiver
Transmitter Configuration Switch and Control Bus Inter-
face
3 1 RECEIVER BLOCK
During normal operation the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Re-
covery Device (DP83231) During the Internal Loopback
mode of operation the Receiver Block accepts data from
the Transmitter Block as input
The Receiver Block performs the following operations
 Converts the incoming data stream from NRZI to NRZ if
necessary
 Decodes the data from 5B to 4B coding
 Converts the serial bit stream into National byte-wide
code
 Compensates for the differences between the upstream
and local clocks
 Decodes Line States
 Detects link errors
Finally the Receiver Block presents data symbol pairs to
the Configuration Switch Block
The Receiver Block consists of the following functional
blocks
NRZI to NRZ Decoder
Shift Register
Framing Logic
Symbol Decoder
Line State Detector
Elasticity Buffer
Link Error Detector
See Figure 3-1
FIGURE 3-1 Receiver Block Diagram
5
TL F 10386 – 3

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DP83251 arduino
3 0 Functional Description (Continued)
3 3 CONFIGURATION SWITCH
The Configuration Switch consists of a set of multiplexors
and latches which allow the PLAYER device to configure
the data paths without the need of external logic The Con-
figuration Switch is controlled through the Configuration
Register (CR)
The Configuration Switch has four internal buses the
A Request bus the B Request bus the Receive bus and
the PHY Invalid bus The two Request buses can be driv-
en by external input data connected to the external PHY
Port Interface The Receive bus is internally connected to
the Receive Block of the PLAYER device while the PHY
Invalid bus has a fixed 10-bit LSU pattern useful during the
connection process The configuration switch also has three
internal multiplexors each can select any of the four buses
to connect to its respective data path The first two are
PHY Port Interface output data paths A Indicate and
B Indicate that can drive output data paths of the external
PHY Port Interface The third output data path is connected
internally to the Transmit Block
The Configuration Switch is the same on both the DP83251
device and the DP83255 device However the DP83255
has two PHY Port interfaces connected to the Configuration
Switch whereas the DP83251 has one PHY Port Interface
The DP83255 uses the A Request and A Indicate paths
as one PHY Port Interface and the B Request and B Indi-
cate paths as the other PHY Port interface (see Figure 3-
5a ) The DP83251 having only one port interface uses the
B Request and A Indicate paths as its external port The
A Request and B Indicate paths of the DP83251 are null
connections and are not used by this device (see Figure 3-
5b )
TL F 10386 – 7
FIGURE 3-5a Configuration Switch Block
Diagram for DP83255
TL F 10386 – 34
FIGURE 3-5b Configuration Switch Block
Diagram for DP83251
11

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