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PDF M368L3313DTL Data sheet ( Hoja de datos )
| Número de pieza | M368L3313DTL | |
| Descripción | 256MB DDR SDRAM MODULE | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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M368L3313DTL
184pin Unbuffered DDR SDRAM MODULE
256MB DDR SDRAM MODULE
(32Mx64(16Mx64*2 bank) based on 16Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.2
May. 2002
Rev. 0.2 May.2002
1 page  
M368L3313DTL
184pin Unbuffered DDR SDRAM MODULE
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
V IN, VOUT
VDD
-0.5 ~ 3.6
-1.0 ~ 3.6
Voltage on VDDQ supply relative to Vss
Storage temperature
Power dissipation
VDDQ
TSTG
PD
-1.0 ~ 3.6
-55 ~ +150
24
Short circuit current
IOS 50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
V
°C
W
mA
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V SS=0V, T A=0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V DD of 2.5V)
I/O Supply voltage
VDD
VDDQ
2.3
2.3
2.7
2.7 V
I/O Reference voltage
V REF
VDDQ/2-50mV VDDQ/2+50mV
V
1
I/O Termination voltage(system)
Input logic high voltage
VTT
V I H(DC)
V REF-0.04
VR E F+ 0 . 1 5
VR E F+ 0 . 0 4
VDDQ +0.3
V
V
2
4
Input logic low voltage
Input Voltage Level, CK and CK inputs
VIL (DC)
V I N(DC)
-0.3
-0.3
V REF-0.15
VDDQ +0.3
V
V
4
Input Differential Voltage, CK and CK inputs
V I D(DC)
0.3
VDDQ +0.6
V
3
Input crossing point voltage, CK and CK inputs
VIX ( D C )
1.15
1.35 V 5
Input leakage current
II -2
2 uA
Output leakage current
Output High Current(Normal strengh driver)
;V OUT = VTT + 0.84V
Output High Current(Normal strengh driver)
;V OUT = VTT - 0.84V
Output High Current(Half strengh driver)
;V OUT = VTT + 0.45V
Output High Current(Half strengh driver)
;V OUT = VTT - 0.45V
IO Z -5
IOH -16.8
IOL 16.8
IOH -9
IOL 9
5 uA
mA
mA
mA
mA
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in V REF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2.VTT is not applied directly to the device. VT T is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.2 May.2002
5 Page 
M368L3313DTL
184pin Unbuffered DDR SDRAM MODULE
Command Truth Table
Register
Register
Refresh
COMMAND
Extended MRS
Mode Register Set
Auto Refresh
Self
Refresh
Entry
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Active Power Down
Entry
Exit
Precharge Power Down Mode
Entry
Exit
DM
No operation (NOP) : Not defined
CKEn-1
H
H
H
L
H
H
H
H
H
H
L
H
L
H
H
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CKEn CS RAS CAS WE BA0,1 A10/AP
A11
A9 ~ A0
X LL L L
OP CODE
X LL L L
OP CODE
H
LL
LH
L
X
LH H H
H
HX
XX
X
X LL HHV
Row Address
L Column
X LH L HV
Address
H (A0~A9)
L Column
X LH L LV
Address
H (A0~A9)
X LH H L
X
V
X LL H L
X
L
H
X
HX
XX
L
LV
VV
X
H XX XX
HX
XX
L
LH H H
HX
XX
H
LV
VV
X
XX
HX
XX
X
LH H H
X
Note
1, 2
1, 2
3
3
3
3
4
4
4
4, 6
7
5
8
9
9
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA 0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA 0 ~ BA1 : Bank select addresses.
If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA 0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA 0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.2 May.2002
11 Page | ||
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