|
|
PDF DP83266 Data sheet ( Hoja de datos )
| Número de pieza | DP83266 | |
| Descripción | MACSITM Device | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DP83266 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
PRELIMINARY
October 1994
DP83266 MACSITM Device
(FDDI Media Access Controller and System Interface)
General Description
The DP83266 Media Access Controller and System Inter-
face (MACSI) implements the ANSI X3T9 5 Standard Media
Access Control (MAC) protocol for operation in an FDDI
token ring and provides a comprehensive System Interface
The MACSI device transmits receives repeats and strips
tokens and frames It produces and consumes optimized
data structures for efficient data transfer Full duplex archi-
tecture with through parity allows diagnostic transmission
and self testing for error isolation and point-to-point connec-
tions
The MACSI device includes the functionality of both the
DP83261 BMACTM device and the DP83265 BSI-2TM device
with additional enhancements for higher performance and
reliability
Features
Y Over 9 kBytes of on-chip FIFO
Y 5 DMA channels (2 Output and 3 Input)
Y 12 5 MHz to 25 MHz operation
Y Full duplex operation with through parity
Y Supports JTAG boundary scan
Y Real-time Void stripping indicator for bridges
Y On-chip address bit swapping capability
Y 32-bit wide Address Data path with byte parity
Y Programmable transfer burst sizes of 4 or 8
32-bit words
Y Receive frame filtering services
Y Frame-per-Page mode controllable on each
DMA channel
Y Demultiplexed Addresses supported on ABus
Y New multicast address matching feature
Y ANSI X3T9 5 MAC standard defined ring
service options
Y Supports all FDDI Ring Scheduling Classes
(Synchronous Asynchronous etc )
Y Supports Individual Group Short Long and
External Addressing
Y Generates Beacon Claim and Void frames
Y Extensive ring and station statistics gathering
Y Extensions for MAC level bridging
Y Enhanced SBus compatibility
Y Interfaces to DRAMs or directly to system bus
Y Supports frame Header Info splitting
Y Programmable Big or Little Endian alignment
Block Diagram
TL F 11705 – 1
FIGURE 1-1 FDDI Chip Set Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
BMACTM BSI-2TM MACSITM and PLAYERaTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11705
RRD-B30M105 Printed in U S A
1 page  
2 0 General Features (Continued)
These paths allow error isolation at the device level
The MACSI device also supports through parity Even when
parity is not used by the system parity support can be pro-
vided across the PHY Interface
2 11 32-BIT ADDRESS DATA PATH TO HOST MEMORY
The MACSI device provides a 32-bit wide synchronous data
interface which permits connection to a standard multi-
master system bus operating from 12 5 MHz to 33 MHz or
to local memory using Big or Little Endian byte ordering
Demultiplexed addresses are provided on dedicated pins
Address information is also multiplexed on the data pins to
provide backward compatibility for designs based on the
BSI device The local memory may be static or dynamic For
maximum performance the MACSI device uses burst mode
transfers with four or eight 32-bit words to a burst To assist
the user with the burst transfer capability the three bits of
the address which cycle during a burst are output as demul-
tiplexed signals Maximum burst speed is one 32-bit word
per clock but slower speeds may be accommodated by in-
serting wait states
The MACSI device can operate within any combination of
cached non-cached paged or non-paged memory environ-
ments To provide this capability all data structures are con-
tained within a page boundary and bus transactions never
cross page boundaries The MACSI device performs all bus
transactions within aligned blocks to ease the interface to a
cached environment
2 12 MULTI-CHANNEL ARCHITECTURE
The MACSI device provides three Input Channels and two
Output Channels which are designed to operate indepen-
dently and concurrently They are separately configured by
the user to manage the reception or transmission of a par-
ticular kind of frame (for example synchronous frames
only)
2 13 SUPPORT FOR HEADER INFO SPLITTING
In order to support high performance protocol processing
the MACSI device can be programmed to split the header
and information portions of (non-MAC SMT) frames be-
tween two Indicate Channels Frame bytes from the Frame
Control field (FC) up to the user-defined header length are
copied onto Indicate Channel 1 and the remaining bytes
(Info) are copied onto Indicate Channel 2 This is useful for
separating protocol headers from data and allows them to
be stored in different regions of memory to prevent unnec-
essary copying In addition a protocol monitor application
may decide to copy only the header portion of each frame
2 14 MAC BRIDGING SUPPORT
Support for bridging and monitoring applications is provided
by the Internal External Sorting Mode All frames matching
the external address (frames requiring bridging) are sorted
onto Indicate Channel 2 MAC and SMT frames matching
the internal (Ring Engine) address are sorted onto Indicate
Channel 0 and all other frames matching the device’s inter-
nal address (short or long) are sorted onto Indicate
Channel 1
2 15 ADDRESS BIT SWAPPING
The MACSI contains the necessary logic for swapping the
address fields within each frame between FDDI and IEEE
Canonical bit order This involves a bit reversal within each
byte of the address field (e g 08-00-17-C2-A1-03 would be-
come 10 00 E8 43 85 C0) This option is selectable on a per
channel basis and is supported on all transmit and receive
channels This is useful for bridging FDDI to Ethernet or for
swapping addresses for higher level protocols
2 16 STATUS BATCHING SERVICES
The MACSI device provides status for transmitted and re-
ceived frames Interrupts to the host are generated only at
status breakpoints which are defined by the user on a per
DMA Channel basis Breakpoints are selected when the
Channel is configured for operation To allow batching the
MACSI provides a status option called Tend that causes
the device to generate a single Confirmation Message De-
scriptor (CNF) for one or more Request Descriptors (REQs)
The MACSI device further reduces host processing time by
separating received frame status from the received data
This allows the CPU to scan quickly for errors when decid-
ing whether further processing should be done on received
frames If status was embedded in the data stream all data
would need to be read contiguously to find the Status Indi-
cator
2 17 RECEIVE FRAME FILTERING SERVICES
To increase performance and reliability the MACSI device
can be programmed to filter out identical MAC (same FC
and Info field) or SMT frames received from the ring Void
frames are filtered out automatically Filtering unnecessary
frames reduces the fill rate of the Indicate FIFO reduces
CPU frame processing time and reduces memory bus
transactions
2 18 TWO TIMING DOMAINS
To provide maximum performance and system flexibility the
MACSI device uses two independent clocks one for the
MAC (ring) Interface and one for the system memory bus
The MACSI device provides a fully synchronized interface
between these two timing domains
2 19 CLUSTERED INTERRUPTS
The MACSI device can be operated in a polled or interrupt-
driven environment The MACSI device provides the ability
to generate attentions (interrupts) at group boundaries
Some boundaries are pre-defined in hardware others are
defined by the user when the Channel is configured This
interrupt scheme significantly reduces the number of inter-
rupts to the host thus reducing host processing overhead
2 20 FIFO MEMORY
The MACSI device contains over 9 kBytes of on-chip FIFO
memory This memory includes separate 4 6 kByte FIFOs
for both the Transmit (Request) and Receive (Indicate) data
paths These data FIFOs allow the MACSI device to support
over 370 ms of bus latency for both transmit and receive
They also allow the MACSI device to buffer entire maximum
length FDDI frames on-chip for both transmit and receive
simultaneously This allows lower cost systems by enabling
the MACSI device to reside directly on system buses with
high latency requirements
These FIFOs support all of the features available in the orig-
inal BSI device including two transmit and three receive
channels to make efficient use of the FIFO resources New
transmit thresholds are available to allow full use of the larg-
er transmit FIFO
5
5 Page 
3 0 Architectural Description (Continued)
FIGURE 3-4 Service Engine BIU Internal Block Diagram
TL F 11705 – 6
Upon receiving the data the Indicate Block performs the
following functions
Decodes the Frame Control field to determine frame type
Sorts received frames onto Channels according to the
Sort Mode
Optionally Filters identical MAC frames
Filters Void frames
Copies the received frames to memory according to
Copy Criteria
Writes status for the received frames to the Indicate
Status Queue
Issues interrupts to the host at host-defined status break-
points
3 4 2 Request Machine
The Request Machine presents frames to the Ring Engine
(MAC) in a byte stream format (MA Request)
The Request Machine performs the following functions
Reads frames from host memory and assembles them
onto Request Channels
Prioritizes active requests
Transmits frames to the Ring Engine (MAC)
Optionally writes status for transmitted and returning
frames
Issues interrupts to the host on user-defined group
boundaries
3 4 3 Status Space Machine
The Status Space Machine is used by both the Indicate Ma-
chine and the Request Machine
The Status Space Machine manages all descriptor Queues
and writes status for received and transmitted frames
3 4 4 Bus Interface Unit
The Bus Interface Unit (BIU) is used by both the Indicate
and Request Blocks It manages the ABus Interface provid-
ing the MACSI device with a 32-bit data path to local or
system memory
The Bus Interface Unit controls the transfer of Data Units
and Descriptors between the MACSI device and Host mem-
ory via the ABus
Data and Descriptors are transferred between the MACSI
device and Host memory Each Channel type handles a set
of Data and Descriptor objects The three Indicate (Receive)
Channels use the following objects
1 Input Data Units (written by MACSI)
2 Input Data Unit Descriptors (written by MACSI)
3 Pool Space Descriptors (read by MACSI)
The two Request (Transmit) Channels each use the follow-
ing objects
1 Output Data Units (read by MACSI)
2 Output Data Unit Descriptors (read by MACSI)
3 Confirmation Message Descriptors (written by MACSI)
4 Request Descriptors (read by MACSI)
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet DP83266.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DP83261 | BMAC Device | National Semiconductor |
| DP83266 | DP83266 MACSI Device (FDDI Media Access Controller and System Interface) (Rev. A) |  Texas Instruments |
| DP83266 | MACSITM Device | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |