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PDF DP83256 Data sheet ( Hoja de datos )
| Número de pieza | DP83256 | |
| Descripción | (DP83256 / DP83257) PLAYER Device | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
October 1994
DP83256 56-AP 57
PLAYERa TM Device (FDDI Physical Layer Controller)
General Description
The DP83256 56-AP 57 Enhanced Physical Layer Control-
ler (PLAYERa device) implements one complete Physical
Layer (PHY) entity as defined by the Fiber Distributed Data
Interface (FDDI) ANSI X3T9 5 standard
The PLAYERa device integrates state of the art digital
clock recovery and improved clock generation functions to
enhance performance eliminate external components and
remove critical layout requirements
FDDI Station Management (SMT) is aided by Link Error
Monitoring support Noise Event Timer (TNE) support Op-
tional Auto Scrubbing support an integrated configuration
switch and built-in functionality designed to remove all strin-
gent response time requirements such as PC React and
CF React
Features
Y Single chip FDDI Physical Layer (PHY) solution
Y Integrated Digital Clock Recovery Module provides en-
hanced tracking and greater lock acquisition range
Y Integrated Clock Generation Module provides all neces-
sary clock signals for an FDDI system from an external
12 5 MHz reference
Y Alternate PMD Interface (DP83256-AP 57) supports
UTP twisted pair FDDI PMDs with no external clock re-
covery or clock generation functions required
Y No External Filter Components
Y Connection Management (CMT) Support (LEM TNE
PC React CF React Auto Scrubbing)
Y Full on-chip configuration switch
Y Low Power CMOS-BIPOLAR design using a single 5V
supply
Y Full duplex operation with through parity
Y Separate management interface (Control Bus)
Y Selectable Parity on PHY-MAC Interface and Control
Bus Interface
Y Two levels of on-chip loopback
Y 4B 5B encoder decoder
Y Framing logic
Y Elasticity Buffer Repeat Filter and Smoother
Y Line state detector generator
Y Supports single attach stations dual attach stations
and concentrators with no external logic
Y DP83256 for SAS DAS single path stations
Y DP83257 for SAS DAS single dual path stations
Y DP83256-AP for SAS DAS single path stations that re-
quire the alternate PMD interface
TL F 11708 – 1
FIGURE 1-1 FDDI Chip Set Overview
TRI-STATE is a registered trademark of National Semiconductor Corporation
BMACTM BSITM CDDTM CDLTM CRDTM CYCLONETM MACSITM PLAYERTM PLAYERaTM and TWISTERTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11708
RRD-B30M115 Printed in U S A
1 page  
2 0 Architecture Description
2 1 BLOCK OVERVIEW
The PLAYERa device is comprised of six blocks Clock
Recovery Receiver Configuration Switch Transmitter Sta-
tion Management (SMT) Support and Clock Generation
Module as shown in Figure 2-1
Clock Recovery
The Clock Recovery Module accepts a 125 Mbps NRZI data
stream from the external PMD receiver It then provides the
extracted and synchronized data and clock to the Receiver
block
The Clock Recovery Module performs the following opera-
tions
Locks to and tracks the incoming NRZI data stream
Extracts data stream and synchronized 125 MHz clock
Receiver
During normal operation the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Re-
covery Module During the Internal Loopback mode of oper-
ation the Receiver Block accepts data directly from the
Transmitter Block
The Receiver Block performs the following operations
Optionally converts the incoming data stream from NRZI
to NRZ
Decodes the data from 5B to 4B coding
Converts the serial bit stream into 10-bit bytes composed
of 8 bits data 1 bit parity and 1 bit control information
Compensates for the differences between the upstream
station clock and the local clocks
Decodes Line States
Detects link errors
Presents data symbol pairs (bytes) to the Configuration
Switch Block
Configuration Switch
An FDDI station may be in one of three configurations Iso-
late Wrap or Thru The Configuration Switch supports these
configurations by switching the transmitted and received
data paths between PLAYERa devices and one or more
MACSI devices
The configuration switch is integrated into the PLAYERa
device therefore no external logic is required for this func-
tion
Setting the Configuration switch can be done explicitly via
the Control Bus Interface or it can be set automatically with
the CF React SMT Support feature
FIGURE 2-1 PLAYERa Device Block Diagram
5
TL F 11708 – 2
5 Page 
3 0 Functional Description (Continued)
Super Idle Line State
The Line State Detector recognizes the incoming data to be
in the Super Idle Line State upon the reception of 8 consec-
utive Idle symbol pairs nominally (plus 1 symbol pair)
The Super Idle Line State is used to insure synchronization
of PCM signalling
No Signal Detect
The Line State Detector recognizes the incoming data to be
in the No Signal Detect state upon the deassertion of the
Signal Detect signal or lack of internal clock detect from the
Clock Recovery Module and reception of 8 Quiet symbol
pairs nominally No Signal Detect indicates that the incom-
ing link is inactive This is the same as receiving Quiet Line
State (QLS)
Master Line State
The Line State Detector recognizes the incoming data to be
in the Master Line State upon the reception of eight consec-
utive Halt-Quiet symbol pairs nominally (plus up to 2 symbol
pairs in start up cases)
The Master Line State is used in the handshaking sequence
of the PHY Connection Management process
Halt Line State
The Line State Detector recognizes the incoming data to be
in the Halt Line State upon the reception of eight consecu-
tive Halt symbol pairs nominally (plus up to 2 symbol pairs in
start up cases)
The Halt Line State is used in the handshaking sequence of
the PHY Connection Management process
Quiet Line State
The Line State Detector recognizes the incoming data to be
in the Quiet Line State upon the reception of eight consecu-
tive Quiet symbol pairs nominally (plus up to 9 bits of 0 in
start up cases)
The Quiet Line State is used in the handshaking sequence
of the PHY Connection Management process
Noise Line State
The Line State Detector recognizes the incoming data to be
in the Noise Line State upon the reception of 16 noise sym-
bol pairs without entering any known line state
The Noise Line State indicates that data is not being re-
ceived correctly
Line State Unknown
The Line State Detector recognizes the incoming data to be
in the Line State Unknown state upon the reception of 1
inconsistent symbol pair (i e data that is not expected) This
may signify the beginning of a new line state
Line State Unknown indicates that data is not being re-
ceived correctly If the condition persists the Noise Line
State (NLS) may be entered
ELASTICITY BUFFER
The Elasticity Buffer performs the function of a ‘‘variable
depth’’ FIFO to compensate for phase and frequency clock
skews between the Receive Clock (RXCg) and the Local
Byte Clock (LBC)
Bit 5 (EBOU) of the Receive Condition Register B (RCRB) is
set to 1 to indicate an error condition when the Elasticity
Buffer cannot compensate for the clock skew
The Elasticity Buffer will support a maximum clock skew of
50 ppm with a maximum packet length of 4500 bytes
To make up for the accumulation of frequency disparity be-
tween the two clocks the Elasticity Buffer will insert or de-
lete Idle symbol pairs in the preamble Data is written into
the byte-wide registers of the Elasticity Buffer with the Re-
ceive Clock while data is read from the registers with the
Local Byte Clock
The Elasticity Buffer will recenter (i e set the read and write
pointers to a predetermined distance from each other) upon
the detection of a JK or every four byte times during PHY
Invalid (i e MLS HLS QLS NLS NSD) and Idle Line State
The Elasticity Buffer is designed such that a given register
cannot be written and read simultaneously under normal op-
erating conditions To avoid metastability problems the EB
overflow event is flagged and the data is tagged before the
over under run actually occurs
LINK ERROR DETECTOR
The Link Error Detector provides continuous monitoring of
an active link (i e during Active and Idle Line States) to
insure that it does not exceed the maximum Bit Error Rate
requirement as set by the ANSI standard for a station to
remain on the ring
Upon detecting a link error the internal 8-bit Link Error Mon-
itor Counter is decremented The start value for the Link
Error Monitor Counter is programmed through the Link Error
Threshold Register (LETR) When the Link Error Monitor
Counter reaches zero bit 4 (LEMT) of the Interrupt Condi-
tion Register (ICR) is set to 1 The current value of the Link
Error Monitor Counter can be read through the Current Link
Error Count Register (CLECR) For higher error rates the
current value is an approximate count because the counter
rolls over
There are two ways to monitor Link Error Rate polling and
interrupt
Polling
The Link Error Monitor Counter can be set to a large value
like FF This will allow for the greatest time between polling
the register This start value is programmed through the Link
Error Threshold Register (LETR)
Upon detecting a link error the Line Error Monitor Counter
is decremented
The Host System reads the current value of the Link Error
Monitor Counter via the Current Link Error Count Register
(CLECR) The Counter is then reset to FF
Interrupt
The Link Error Monitor Counter can be set to a small value
like 5 to 10 This start value is programmed through the Link
Error Threshold Register (LETR)
Upon detecting a link error the Line Error Monitor Counter
is decremented When the counter reaches zero bit 4
(LEMT) of the Interrupt Condition Register (ICR) is set to 1
and the interrupt signal goes low interrupting the Host Sys-
tem
Miscellaneous Items
When bit 0 (RUN) of the Mode Register (MR) is set to zero
or when the PLAYERa device is reset through the Reset
pin (ERST) the internal signal detect line is internally
forced to zero and the Line State Detector is set to Line
State Unknown and No Signal Detect
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet DP83256.PDF ] | |
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