|
|
PDF CAT9555 Data sheet ( Hoja de datos )
| Número de pieza | CAT9555 | |
| Descripción | 16-Bit I2C and SMBus I/O Port | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CAT9555 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
CAT9555
16-bit I2C and SMBus I/O Port with Interrupt
FEATURES
I 400kHz I2C bus compatible*
I 2.3V to 5.5V operation
I Low stand-by current
I 5V tolerant I/Os
I 16 I/O pins that default to inputs at power-up
I High drive capability
I Individual I/O configuration
I Polarity inversion register
I Active low interrupt output
I Internal power-on reset
I No glitch on power-up
I Noise filter on SDA/SCL inputs
I Cascadable up to 8 devices
I Industrial temperature range
I RoHS-compliant 24-lead SOIC and TSSOP, and
24-pad TQFN (4 x 4 mm) packages
APPLICATIONS
I White goods (dishwashers, washing machines)
I Handheld devices (cell phones, PDAs, digital
cameras)
I Data Communications (routers, hubs and
servers)
DESCRIPTION
The CAT9555 is a CMOS device that provides 16-bit
parallel input/output port expansion for I2C and SMBus
compatible applications. These I/O expanders provide
a simple solution in applications where additional I/Os
are needed: sensors, power switches, LEDs,
pushbuttons, and fans.
The CAT9555 consists of two 8-bit Configuration ports
(input or output), Input, Output and Polarity inversion
registers, and an I2C/SMBus-compatible serial interface.
Any of the sixteen I/Os can be configured as an input or
output by writing to the configuration register. The system
master can invert the CAT9555 input data by writing to
the active-high polarity inversion register.
The CAT9555 features an active low interrupt output
which indicates to the system master that an input state
has changed.
The three address input pins provide the device's
extended addressing capability and allow up to eight
devices to share the same bus. The fixed part of the I2C
slave address is the same as the CAT9554, allowing up
to eight of these devices in any combination to be
connected on the same bus.
For Ordering Information details, see page 16.
BLOCK DIAGRAM
A0
A1
A2
SCL
SDA
VCC
VCC
INPUT
FILTER
POWER-ON
RESET
I2C/SMBUS
CONTROL
8-BIT
INPUT/
OUTPUT
PORTS
WRITE pulse
READ pulse
I/O1.0
I/O1.1
I/O1.2
I/O1.3
I/O1.4
I/O1.5
I/O1.6
I/O1.7
8-BIT
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
LP FILTER
~
I/O0.0
I/O0.1
I/O0.2
I/O0.3
I/O0.4
I/O0.5
I/O0.6
I/O0.7
VINT
INT
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 8551, Rev. D
1 page  
www.DataSheet4U.com
CAT9555
A.C. CHARACTERISTICS
VCC = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise specified (Note 1).
Symbol Parameter
fSCL
tSP
tLOW
tHIGH
(2)
tR
(2)
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tAA
tDH
(2)
tBUF
Port Timing
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data In Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
tPV Output Data Valid
tPS Input Data Setup Time
tPH Input Data Hold Time
Interrupt Timing
tIV Interrupt Valid
tIR Interrupt Reset
Min
1.3
0.6
20
20
0.6
0.6
0
100
0.6
50
1.3
100
1
Max
400
50
300
300
900
200
4
4
Notes:
1. Test conditions according to "AC Test Conditions" table.
2. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
Units
kHz
ns
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
ns
ns
µs
µs
µs
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 8551, Rev. D
5 Page 
www.DataSheet4U.com
CAT9555
The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Bit values in this register have no effect on I/O
pins defined as inputs. Reads from the output port
register reflect the value that is in the flip-flop controlling
the output, not the actual I/O pin value.
The polarity inversion register allows the user to invert
the polarity of the input port register data. If a bit in this
register is set (“1”) the corresponding input port data is
inverted. If a bit in the polarity inversion register is
cleared (“0”), the original input port polarity is retained.
The configuration register sets the directions of the
ports. Set the bit in the configuration register to enable
the corresponding port pin as an input with a high
impedance output driver. If a bit in this register is cleared,
the corresponding port pin is enabled as an output. At
power-up, the I/Os are configured as inputs with a weak
pull-up resistor to VCC.
Writing to the Port Registers
Data is transmitted to the CAT9555 registers using the
write mode shown in Figure 8 and Figure 9.
The CAT9555 registers are configured to operate at four
register pairs: Input Ports, Output Ports, Polarity Inver-
sion Ports and Configuration Ports. After sending data to
one register, the next data byte will be sent to the other
register in the pair. For example, if the first byte of data
is sent to the Configuration Port 1 (register 7), the next
byte will be stored in the Configuration Port 0 (register 6).
Each 8-bit register may be updated independently of the
other registers.
Reading the Port Registers
The CAT9555 registers are read according to the timing
diagrams shown in Figure 10 and Figure 11. Data from
the register, defined by the command byte, will be sent
serially on the SDA line. Data is clocked into the register
on the failing edge of the acknowledge clock pulse. After
the first byte is read, additional data bytes may be read,
but the second read will reflect the data from the other
register in the pair. For example, if the first read is data
from Input Port 0, the next read data will be from Input
Port 1. The transfer is stopped when the master will not
acknowledge the data byte received and issue the
STOP condition.
SCL
1 23 4 56 78 9
slave address
command byte
data to port 0
SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7
DATA 0
start condition
R/W acknowledge
from slave
acknowledge
from slave
WRITE TO
PORT
DATA OUT
FROM PORT 0
DATA OUT
FROM PORT 1
data to port 1
0.0 A 1.7
DATA 1
acknowledge
from slave
1.0 A P
stop
condition
tpv
DATA VALID
tpv
Figure 8. Write to Output Port Registers
SCL
1 2 3 4 56 7 8 9 1 2 3 4 5 6 78 9 1 2 3 4 56 7 8 9 1 2 3 4 5
slave address
command byte
data to configuration 0
data to configuration 1
SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0A 1 1 0 A MSB
DATA 0
start condition
R/W acknowledge
from slave
acknowledge
from slave
LSB A MSB
DATA 1
acknowledge
from slave
LSB A P
Figure 9. Write to Configuration Registers
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 8551, Rev. D
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CAT9555.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CAT9552 | 16-Channel I2C-bus LED Driver |  ON Semiconductor |
| CAT9554 | 8-Bit I2C and SMBus I/O Port | Catalyst Semiconductor |
| CAT9554A | 8-Bit I2C and SMBus I/O Port | Catalyst Semiconductor |
| CAT9555 | 16-Bit I2C and SMBus I/O Port | Catalyst Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |