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Número de pieza | PCA9539 | |
Descripción | 16-bit I2C and SMBus low power I/O port | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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INTEGRATED CIRCUITS
PCA9539
16-bit I2C and SMBus, low power I/O port
with interrupt and reset
Product data sheet
Supersedes data of 2004 Aug 27
2004 Sep 30
Philips
Semiconductors
1 page Philips Semiconductors
16-bit I2C and SMBus, low power I/O port
with interrupt and reset
Product data sheet
PCA9539
SIMPLIFIED SCHEMATIC OF I/Os
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE CONFIGURATION
PULSE
WRITE PULSE
CONFIGURATION
REGISTER
DQ
FF
CK Q
READ PULSE
DQ
FF
CK Q
OUTPUT
PORT
REGISTER
Q1
INPUT PORT
REGISTER
DQ
FF
CK Q
Q2
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
DQ
FF
CK Q
POLARITY
INVERSION
REGISTER
NOTE: At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/Os
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input. The input voltage may be raised
above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on,
depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance path that exists between the
pin and either VDD or VSS.
OUTPUT PORT
REGISTER DATA
VDD
ESD PROTECTION DIODE
I/O PIN
ESD PROTECTION DIODE
VSS
INPUT PORT
REGISTER DATA
TO INT
POLARITY
REGISTER DATA
SU02203
2004 Sep 30
5
5 Page Philips Semiconductors
16-bit I2C and SMBus, low power I/O port with interrupt
Product data sheet
PCA9539
TYPICAL APPLICATION
VDD
(5 V)
VDD 10 kΩ 10 kΩ 10 kΩ 10 kΩ
SCL
MASTER
CONTROLLER
SDA
INT
RESET
GND
VDD
SCL
SDA
INT
RESET
2 kΩ
I/O0.0
I/O0.1
I/O0.2
I/O0.3
I/O0.4
I/O0.5
PCA9539
I/O0.6
I/O0.7
I/O1.0
I/O1.1
A1 I/O1.2
I/O1.3
A0 I/O1.4
I/O1.5
I/O1.6
VSS I/O1.7
100 kΩ
(×3)
SUBSYSTEM 1
(e.g. temp sensor)
INT
SUBSYSTEM 2
(e.g. counter)
RESET
A
ALARM
SUBSYSTEM 3
(e.g. alarm system)
ENABLE
B
Controlled Switch
(e.g. CBT device)
VDD
10 DIGIT
NUMERIC
KEYPAD
NOTE: Device address configured as 1110100 for this example
I/O0.0, I/O0.2, I/O0.3, configured as outputs
I/O0.1, I/O0.4, I/O0.5, configured as inputs
I/O0.6, I/O0.7, and I/O1.0 to I/O1.7 configured as inputs
Figure 11. Typical application
SW02094
Minimizing IDD when the I/O is used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 11. Since the LED acts as a
diode, when the LED is off the I/O VIN is about 1.2 V less than VDD. The supply current, IDD, increases as VIN becomes lower than VDD and is
specified as ∆IDD in the DC characteristics table.
Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or
equal to VDD when the LED is off. Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VDD and prevents additional supply current consumption when
the LED is off.
VDD
3.3 V
5V
VDD
LEDx
LED
100 kΩ
SW02086
Figure 12. High value resistor in parallel with the LED
2004 Sep 30
11
VDD
LEDx
LED
SW02087
Figure 13. Device supplied by a lower voltage
11 Page |
Páginas | Total 21 Páginas | |
PDF Descargar | [ Datasheet PCA9539.PDF ] |
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