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PDF IDT74LVCR16952A Data sheet ( Hoja de datos )
| Número de pieza | IDT74LVCR16952A | |
| Descripción | 16-BIT REGISTERED TRANSCEIVER | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDT74LVCR16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
3.3V CMOS 16-BIT
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
INDUSTRIALTEMPERATURERANGE
IDT74LVCR16952A
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in TSSOP package
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
This 16-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power device is organized as two
independent 8-bit D-type registered transceivers with separate input and
output control for independent control of data flow in either direction. For
example, the A-to-B Enable (CEAB) must be LOW to enter data from the A
port.CLKABcontrolstheclockingfunction. WhenCLKABtogglesfromLOW-
to-HIGH, the data present on the A port will be clocked into the register.
OEAB performs the output enable function on the B port. Data flow from the
B port to A port is similar but requires using CEBA, CLKBA, andOEBA inputs.
Full 16-bit operation is achieved by tying the control pins of the independent
transceivers together.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCR162952A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads.This
driver has been developed to drive ±12mA at the designated threshold
levels.
FUNCTIONAL BLOCK DIAGRAM
54
1CEBA
1CLKBA 55
1
1OEAB
3
1CEAB
1CLKAB 2
56
1OEBA
1A1 5
C
CE
D
C
CE
D
31
2CEBA
2CLKBA 30
28
2OEAB
26
2CEAB
2CLKAB 27
29
2OEBA
52 1B1
2A1 15
C
CE
D
C
CE
D
42 2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
1
JANUARY 2004
DSC-4484/2
1 page  
IDT74LVCR16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
VIN
Pulse (1, 2)
Generator
VCC
VOUT
D.U.T.
500Ω
VLOAD
Open
GND
RT
500Ω
CL
Test Circuit for All Outputs
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
LVC Link
Propagation Delay
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
VLOAD/2
VT
tPHZ
VT
0V
VIH
VT
0V
VLOAD/2
VLZ
VOL
VOH
VHZ
0V
LVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tREM
tSU tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
VT
VT
LVC Link
Pulse Width
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74LVCR16952A.PDF ] | |
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