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PDF IDT71V428S Data sheet ( Hoja de datos )

Número de pieza IDT71V428S
Descripción CMOS Static RAM
Fabricantes IDT 
Logotipo IDT Logotipo



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3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
IDT71V428S
IDT71V428L
Features
1M x 4 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Available in 32-pin, 400 mil plastic SOJ package.
Functional Block Diagram
Description
The IDT71V428 is a 4,194,304-bit high-speed Static RAM orga-
nized as 1M x 4. It is fabricated using IDT’s high-perfomance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs.
The IDT71V428 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs
and outputs of the IDT71V428 are LVTTL-compatible and operation is
from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V428 is packaged in a 32-pin, 400 mil Plastic SOJ.
A0
A19
ADDRESS
DECODER
4,194,304-BIT
MEMORY ARRAY
I/O0 – I/O3
4
4
WE
OE CONTROL
CS LOGIC
©2004 Integrated Device Technology, Inc.
1
I/O CONTROL
4
3623 drw 01
SEPTEMBER 2004
DSC-3623/06

1 page




IDT71V428S pdf
IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM
4 Meg (1M x 4-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
Symbol
Parameter
READ CYCLE
tRC Read Cycle Time
tAA Address Access Time
tACS Chip Select Access Time
tCLZ (1 )
Chip Select to Output in Low-Z
tCHZ(1)
Chip Deselect to Output in High-Z
tOE Output Enable to Output Valid
tOLZ(1)
Output Enable to Output in Low-Z
tOHZ(1)
Output Disable to Output in High-Z
tOH Output Hold from Address Change
tPU(1) Chip Select to Power Up Time
tPD(1) Chip Deselect to Power Down Time
WRITE CYCLE
tWC Write Cycle Time
tAW Address Valid to End of Write
tCW Chip Select to End of Write
tAS Address Set-up Time
tWP Write Pulse Width
tWR Write Recovery Time
tDW Data Valid to End of Write
tDH Data Hold Time
tOW(1)
Output Active from End of Write
tWHZ(1)
Write Enable to Output in High-Z
71V428S/L10(2)
Min. Max.
10 ____
____ 10
____ 10
4 ____
5____
5____
0 ____
5____
4 ____
0 ____
____ 10
10 ____
8 ____
8 ____
0 ____
8 ____
0 ____
6 ____
0 ____
3 ____
6____
NOTES:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
2. 0°C to +70°C temperature range only for low power 10ns (L10) speed grade.
71V428S/L12
Min. Max.
12 ____
____ 12
____ 12
4 ____
6____
6____
0 ____
6____
4 ____
0 ____
____ 12
12 ____
8 ____
8 ____
0 ____
8 ____
0 ____
6 ____
0 ____
3 ____
7____
71V428S/L15
Min. Max.
Unit
15 ____ ns
____ 15 ns
____ 15 ns
4 ____ ns
____ 7 ns
____ 7 ns
0 ____ ns
____ 7 ns
4 ____ ns
0 ____ ns
____ 15 ns
15 ____ ns
10 ____ ns
10 ____ ns
0 ____ ns
10 ____ ns
0 ____ ns
7 ____ ns
0 ____ ns
3 ____ ns
____ 7 ns
3623 tbl 10
6.542

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