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PDF DP83849C Data sheet ( Hoja de datos )

Número de pieza DP83849C
Descripción Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! DP83849C Hoja de datos, Descripción, Manual

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August 2006
DP83849C PHYTER® DUAL Commercial Temperature
Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver
General Description
Features
The number of applications requiring Ethernet Con-
nectivity continues to expand. Along with this
increased market demand is a change in application
requirements. Where single channel Ethernet used to
be sufficient, many applications such as wireless
remote base stations and industrial networking now
require DUAL Port functionality for redundancy or sys-
tem management.
The DP83849C is a highly reliable, feature rich device
perfectly suited for commercial or industrial applica-
tions enabling Ethernet on the factory floor. The
DP83849C features two fully independent 10/100 ports
for multi-port applications.
The DP83849C provides optimum flexibility in MPU
selection by supporting both MII and RMII interfaces.
In addition this device includes a powerful new diag-
nostics tool to ensure initial network operation and
maintenance. In addition to the TDR scheme, com-
monly used for detecting faults during installation,
NATIONAL’s innovative cable diagnostics provides for
real time continuous monitoring of the link quality. This
allows the system designer to implement a fault pre-
diction mechanism to detect and warn of changing or
deteriorating link conditions.
With the DP83849C, National Semiconductor contin-
ues to build on its Ethernet expertise and leadership
position by providing a powerful combination of fea-
tures and flexibility, easing Ethernet implementation for
the system designer.
Low-power 3.3V, 0.18µm CMOS technology
Low power consumption <600mW Typical
3.3V MAC Interface
Auto-MDIX for 10/100 Mb/s
Energy Detection Mode
Dynamic Integrity Utility
Dynamic Link Quality Monitoring
TDR based Cable Diagnostic and Cable Length Detection
Optimized Latency for Real Time Ethernet Operation
Reference Clock out
RMII Rev. 1.2 Interface (configurable)
SNI Interface (configurable)
MII Serial Management Interface (MDC and MDIO)
IEEE 802.3u MII
IEEE 802.3u Auto-Negotiation and Parallel Detection
IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
Integrated ANSI X3.263 compliant TP-PMD physical sub-layer
with adaptive equalization and Baseline Wander compensation
Programmable LED support for Link, 10 /100 Mb/s Mode, Activ-
ity, Duplex and Collision Detect
Single register access for complete PHY status
10/100 Mb/s packet BIST (Built in Self Test)
80-pin TQFP package (12mm x 12mm)
Applications
Medical Instrumentation
Factory Automation
Motor & Motion Control
Wireless Remote Base Station
General Embedded Applications
System Diagram
MPU/CPU
MII/RMII/SNI
MII/RMII/SNI
Port B
DP83849C
Port A
25 MHz
Clock
Source
Status
LEDs
Typical Application
PHYTER is a registered trademark of National Semiconductor Corporation
© 2006 National Semiconductor Corporation
1
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10BASE-T
or
100BASE-TX
10BASE-T
or
100BASE-TX
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7.2.2 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2.3 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2.4 RMII and Bypass Register (RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.5 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.2.6 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.2.7 10 Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.2.8 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.2.9 Phy Control Register 2 (PHYCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.2.10 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.3 Link Diagnostics Registers - Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h . . . . . . . . . . . . . . . . . 70
7.3.2 100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h . . . . . . . . . 70
7.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3.4 TDR Window Register (TDR_WIN), Page 2, address 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.3.5 TDR Peak Register (TDR_PEAK), Page 2, address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.3.6 TDR Threshold Register (TDR_THR), Page 2, address 19h . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah . . . . . . . . . . . . . . . . . . . . . . 73
7.3.8 Variance Data Register (VAR_DATA), Page 2, address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . 73
7.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3.10 Link Quality Data Register (LQDR), Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.1 DC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
8.2 AC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.2.6 100BASE-TX MII Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.2.7 100BASE-TX MII Transmit Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.2.9 100BASE-TX MII Receive Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.2.10 100BASE-TX MII Receive Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.2.13 10 Mb/s Serial Mode Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.2.14 10 Mb/s Serial Mode Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.2.15 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2.16 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2.17 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.2.18 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.2.19 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.2.20 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.2.21 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.2.23 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.2.24 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.2.25 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.2.26 RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.2.27 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.2.28 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.2.29 CLK2MAC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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1.3 Clock Interface
Signal Name
X1
X2
CLK2MAC
Type
I
O
O
Pin #
70
69
68
Description
CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock
reference input for the DP83849C and must be connected to a 25
MHz 0.005% (+50 ppm) clock source. The DP83849C supports
either an external crystal resonator connected across pins X1 and
X2, or an external CMOS-level oscillator source connected to pin
X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock refer-
ence input for the RMII mode and must be connected to a 50 MHz
0.005% (+50 ppm) CMOS-level oscillator source.
CRYSTAL OUTPUT: This pin is the primary clock reference out-
put to connect to an external 25 MHz crystal resonator device.
This pin must be left unconnected if an external CMOS oscillator
clock source is used.
CLOCK TO MAC:
In MII mode, this pin provides a 25 MHz clock output to the sys-
tem.
In RMII mode, this pin provides a 50 MHz clock output to the sys-
tem.
This allows other devices to use the reference clock from the
DP83849C without requiring additional clock sources.
If the system does not require the CLK2MAC signal, the
CLK2MAC output should be disabled via the CLK2MAC disable
strap.
1.4 LED Interface
The DP83849C supports three configurable LED pins. The
LEDs support two operational modes which are selected
by the LED mode strap and a third operational mode which
is register configurable. The definitions for the LEDs for
each mode are detailed below. Since the LEDs are also
used as strap options, the polarity of the LED output is
dependent on whether the pin is pulled up or down.
Signal Name
LED_LINK_A
LED_LINK_B
LED_SPEED_A
LED_SPEED_B
LED_ACT/LED_COL_A
LED_ACT/LED_COL_B
Type
I/O
I/O
I/O
Pin #
19
43
20
42
21
41
Description
LINK LED: In Mode 1, this pin indicates the status of the LINK.
The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit
and receive activity in addition to the status of the Link. The LED
will be ON when Link is good. It will blink when the transmitter or
receiver is active.
SPEED LED: The LED is ON when device is in 100 Mb/s and OFF
when in 10 Mb/s. Functionality of this LED is independent of mode
selected.
ACTIVITY LED: In Mode 1, this pin is the Activity LED which is
ON when activity is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indi-
cates Collision detection. For Mode 3, this LED output may be
programmed to indicate Full-duplex status instead of Collision.
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