PDF IDT72T72105 Data sheet ( Hoja de datos )

Número de pieza	IDT72T72105
Descripción	(IDT72T72xxx) 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
Fabricantes	Integrated Device Technology
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No Preview Available ! www.DataSheet4U.com 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 IDT72T7285, IDT72T7295, IDT72T72105, IDT72T72115 FEATURES: • Choose among the following memory organizations: IDT72T7285  16,384 x 72 IDT72T7295  32,768 x 72 IDT72T72105  65,536 x 72 IDT72T72115  131,072 x 72 • Up to 225 MHz Operation of Clocks • User selectable HSTL/LVTTL Input and/or Output • Read Enable & Read Clock Echo outputs aid high speed operation • User selectable Asynchronous read and/or write port timing • 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage • 3.3V Input tolerant • Mark & Retransmit, resets read pointer to user marked position • Write Chip Select (WCS) input disables Write Port HSTL inputs • Read Chip Select (RCS) synchronous to RCLK • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets • Program programmable flags by either serial or parallel means • Selectable synchronous/asynchronous timing modes for Almost- Empty and Almost-Full flags • Separate SCLK input for Serial programming of flag offsets • User selectable input and output port bus-sizing - x72 in to x72 out - x72 in to x36 out - x72 in to x18 out - x36 in to x72 out - x18 in to x72 out • Big-Endian/Little-Endian user selectable byte representation • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Empty, Full and Half-Full flags signal FIFO status • Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) • Output enable puts data outputs into high impedance state • JTAG port, provided for Boundary Scan function • Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA) • Easily expandable in depth and width • Independent Read and Write Clocks (permit reading and writing simultaneously) • High-performance submicron CMOS technology • Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM WEN WCLK/WR WCS D0 -Dn (x72, x36 or x18) LD SEN SCLK INPUT REGISTER OFFSET REGISTER ASYW BE IP BM IW OW MRS PRS TCK TRST TMS TDO TDI Vref WHSTL RHSTL SHSTL WRITE CONTROL LOGIC WRITE POINTER CONTROL LOGIC BUS CONFIGURATION RESET LOGIC JTAG CONTROL (BOUNDARY SCAN) RAM ARRAY 16,384 x 72 32,768 x 72 65,536 x 72 131,072 x 72 OUTPUT REGISTER HSTL I/0 CONTROL OE Q0 -Qn (x72, x36 or x18) FLAG LOGIC READ POINTER FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 READ CONTROL LOGIC RT MARK ASYR EREN ERCLK RCLK/RD REN RCS 5994 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. SEPTEMBER 2003 DSC-5994/12 1 page IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PARTIAL RESET (PRS) MASTER RESET (MRS) WRITE CLOCK (WCLK/WR) WRITE ENABLE (WEN) WRITE CHIP SELECT (WCS) LOAD (LD) (x72, x36, x18) DATA IN (D0 - Dn) SERIAL CLOCK (SCLK) SERIAL ENABLE(SEN) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) FULL FLAG/INPUT READY (FF/IR) PROGRAMMABLE ALMOST-FULL (PAF) IDT 72T7285 72T7295 72T72105 72T72115 READ CLOCK (RCLK/RD) READ ENABLE (REN) OUTPUT ENABLE (OE) READ CHIP SELECT (RCS) (x72, x36, x18) DATA OUT (Q0 - Qn) RCLK ECHO, ERCLK REN ECHO, EREN MARK RETRANSMIT (RT) EMPTY FLAG/OUTPUT READY (EF/OR) PROGRAMMABLE ALMOST-EMPTY (PAE) HALF-FULL FLAG (HF) BIG-ENDIAN/LITTLE-ENDIAN (BE) INTERSPERSED/ NON-INTERSPERSED PARITY (IP) INPUT WIDTH (IW) BUS- OUTPUT WIDTH (OW) MATCHING (BM) 5994 drw03 Figure 1. Single Device Configuration Signal Flow Diagram TABLE 1 — BUS-MATCHING CONFIGURATION MODES BM I W OW Write Port Width LL HL HL HH HH L L H L H x72 x72 x72 x36 x18 NOTE: 1. Pin status during Master Reset. Read Port Width x72 x36 x18 x72 x72 5 5 Page IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS — ASYNCHRONOUS TIMING (Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C) Commercial Com’l & Ind’l Commercial IDT72T7285L4-4 IDT72T7295L4-4 IDT72T72105L4-4 IDT72T72115L4-4 IDT72T7285L5 IDT72T7295L5 IDT72T72105L5 IDT72T72115L5 IDT72T7285L6-7 IDT72T7295L6-7 IDT72T72105L6-7 IDT72T72115L6-7 IDT72T7285L10 IDT72T7295L10 IDT72T72105L10 IDT72T72115L10 Symbol fA tAA tCYC tCYH tCYL tRPE tFFA tEFA tPAFA tPAEA tOLZ tOE tOHZ tHF Parameter Cycle Frequency (Asynchronous) Data Access Time Cycle Time Cycle HIGH Time Cycle LOW Time Read Pulse after EF HIGH Clock to Asynchronous FF Clock to Asynchronous EF Clock to Asynchronous Programmable Almost-Full Flag Clock to Asynchronous Programmable Almost-Empty Flag Output Enable to Output in Low Z(1) Output Enable to Output Valid Output Enable to Output in High Z(1) Clock to HF Min. Max. Min. Max. Min. Max. Min. Max. Unit — 100 — 83 — 66 — 50 MHz 0.6 8 0.6 10 0.6 12 0.6 14 ns 10 — 12 — 15 — 20 — ns 4.5 — 5 — 7 — 8 — ns 4.5 — 5 — 7 — 8 — ns 8 — 10 — 12 — 14 — ns — 8 — 10 — 12 — 14 ns — 8 — 10 — 12 — 14 ns — 8 — 10 — 12 — 14 ns — 8 — 10 — 12 — 14 ns 0 — 0 — 0— 0 — ns — 3.4 — 3.6 — 3.8 — 4.5 ns — 3.4 — 3.6 — 3.8 — 4.5 ns — 8 — 10 — 12 — 14 ns NOTES: 1. Values guaranteed by design, not currently tested. 2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order. 11 11 Page

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