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PDF IDT72T1875 Data sheet ( Hoja de datos )

Número de pieza IDT72T1875
Descripción (IDT72T18xxx) HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
Fabricantes IDT 
Logotipo IDT Logotipo



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2.5 VOLT HIGH-SPEED TeraSync™ FIFO
18-BIT/9-BIT CONFIGURATIONS
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,
16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,
IDT72T1845, IDT72T1855
IDT72T1865, IDT72T1875
IDT72T1885, IDT72T1895
IDT72T18105, IDT72T18115
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9
IDT72T18125
FEATURES:
Choose among the following memory organizations:
IDT72T1845 2,048 x 18/4,096 x 9
IDT72T1855 4,096 x 18/8,192 x 9
IDT72T1865 8,192 x 18/16,384 x 9
IDT72T1875 16,384 x 18/32,768 x 9
IDT72T1885 32,768 x 18/65,536 x 9
IDT72T1895 65,536 x 18/131,072 x 9
IDT72T18105 131,072 x 18/262,144 x 9
IDT72T18115 262,144 x 18/524,288 x 9
IDT72T18125 524,288 x 18/1,048,576 x 9
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)
PlasticBall Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK/WR
D0 -Dn (x18 or x9)
LD SEN SCLK
WCS
INPUT REGISTER
OFFSET REGISTER
ASYW
BE
IP
WRITE CONTROL
LOGIC
WRITE POINTER
CONTROL
LOGIC
RAM ARRAY
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
524,288 x 18 or 1,048,576 x 9
FLAG
LOGIC
READ POINTER
IW
OW
MRS
PRS
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
TDI
Vref
WHSTL
RHSTL
SHSTL
HSTL I/0
CONTROL
OE
Q0 -Qn (x18 or x9)
EREN
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
RT
MARK
ASYR
RCLK/RD
REN
RCS
5909 drw01
SEPTEMBER 2003
DSC-5909/16

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IDT72T1875 pdf
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x18) and read
out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8 during the parallel
programming of the flag offsets. If Non-Interspersed Parity mode is selected,
then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode
is selected during Master Reset by the state of the IP input pin. This mode is
relevant only when the input width is set to x18 mode.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 are fabricated using IDT’s high speed sub-
micron CMOS technology.
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IDT72T1875 arduino
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
Parameter
Min.
ILI
ILO
VOH(5)
VOL
Input Leakage Current
Output Leakage Current
Output Logic “1” Voltage,
Output Logic “0” Voltage,
IOH = –8 mA
IOH = –8 mA
IOH = –8 mA
IOL = 8 mA
IOL = 8 mA
IOL = 8 mA
@VDDQ = 2.5V ± 0.125V (LVTTL)
@VDDQ = 1.8V ± 0.1V (eHSTL)
@VDDQ = 1.5V ± 0.1V (HSTL)
@VDDQ = 2.5V ± 0.125V (LVTTL)
@VDDQ = 1.8V ± 0.1V (eHSTL)
@VDDQ = 1.5V ± 0.1V (HSTL)
–10
–10
VDDQ -0.4
VDDQ -0.4
VDDQ -0.4
IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895
Max.
10
10
0.4V
0.4V
0.4V
Unit
µA
µA
V
V
V
V
V
V
ICC1(1,2)
ICC2(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
I/O = HSTL
I/O = eHSTL
IDT72T18105/72T18115/72T18125
— 40 mA
— 60 mA
— 60 mA
— 10 mA
— 50 mA
— 50 mA
ICC1(1,2)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
— 50 mA
— 70 mA
— 70 mA
ICC2(1)
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
I/O = HSTL
I/O = eHSTL
— 20 mA
— 60 mA
— 60 mA
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. For the IDT72T18105/72T18115/72T18125, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 1.0 x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (1.0 x fs), fs = WCLK = RCLK frequency (in MHz)
For the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz).
3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)
with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000
fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,
N= Number of outputs switching.
4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).
5. Outputs are not 3.3V tolerant.
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