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PDF L6382D Data sheet ( Hoja de datos )

Número de pieza L6382D
Descripción Power management unit
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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General features
Integrated high-voltage start-up
4 drivers for PFC, half-bridge & pre-heating
MOSFETs
3.3V microcontroller compatible
Fully integrate power management for all
operating modes
Internal two point VCC regulator
Over-current protection with digital output
signal
Cross-conduction protection (interlocking)
Under voltage lock-out
Integrated bootstrap diode
Applications
Dimmable / non-dimmable ballast
Block diagram
L6382D
Power management unit
for microcontrolled ballast
SO-20
Description
The L6382D is suitable for microcontrolled
electronic ballasts embedding a PFC stage and a
half-bridge stage. The L6382D includes 4
MOSFET driving stages (for the PFC, for the half
bridge, for the preheating MOSFET) plus a power
management unit (PMU) featuring also a
reference able to supply the microcontroller in any
condition.
Besides increasing the application efficiency, the
L6382D reduces the bill of materials because
different tasks (regarding drivers and power
management) are performed by a single IC, which
improves the application reliability.
µ
May 2006
Rev 5
1/22
www.st.com
22

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L6382D pdf
L6382D
Pin settings
Table 1. Pin description
Name Pin N°
Description
Low Side Driver Output. This pin must be connected to the gate of the half-
bridge low side power MOSFET. A resistor connected between this pin and the
power MOS gate can be used to reduce the peak current.
9 LSG An internal 20Kresistor toward ground avoids spurious and undesired
MOSFET turn-on.
The totem pole output stage is able to drive power with a peak current of
120mA source and 120mA sink.
10 Vcc Supply Voltage for the signal part of the IC and for the drivers.
High-side gate-drive floating supply Voltage. The bootstrap capacitor
11
BOOT
connected between this pin and pin 13 (OUT) is fed by an internal
synchronous bootstrap diode driven in phase with the low-side gate-drive. This
patented structure normally replaces the external diode.
High Side Driver Output. This pin must be connected to the gate of the half
bridge high side power MOSFET . A resistor connected between this pin and
the power MOS gate can be used to reduce the peak current.
12 HSG An internal 20Kresistor toward OUT pin avoids spurious and undesired
MOSFET turn-on
The totem pole output stage is able to drive the power MOS with a peak
current of 120mA source and 120mA sink.
High-side gate-drive floating ground. Current return for the high-side gate-drive
13 OUT current. Layout carefully the connection of this pin to avoid too large spikes
below ground.
14 N.C. Not connected
High-voltage start-up. The current flowing into this pin charges the capacitor
connected between pin Vcc and GND to start up the IC. Whilst the chip is in
save mode, the generator is cycled on-off between turn-on and save mode
15 HVSU voltages. When the chip works in operating mode the generator is shut down
and it is re-enabled when the Vcc voltage falls below the UVLO threshold.
According to the required VREF pin current, this pin can be connected to the
rectified mains voltage either directly or through a resistor.
High-voltage spacer. The pin is not connected internally to isolate the high-
16 N.C. voltage pin and comply with safety regulations (creepage distance) on the
PCB.
Output for the HEI block; this driver can be used to drive the MOS employed in
17 HEG isolated filaments preheating. An internal 20Kresistor toward ground avoids
spurious and undesired MOSFET turn-on.
Output of current sense comparator, compatible with TTL logic signal; during
18 CSO operating mode, the pin is forced low whereas whenever the OC comparator is
triggered (CSI> 0.5V typ.) the pin latches high.
Input of current sense comparator, it is enabled only during operating mode;
19
CSI
when the pin voltage exceeds the internal threshold, the CSO pin is forced
high and the half bridge drivers are disabled. It exits from this condition by
either cycling the Vcc below the UVLO or with LGI=HGI=low simultaneously.
Voltage reference. During normal mode an internal generator provides an
accurate voltage reference that can be used to supply up to 30mA (during
20 VREF operating mode) to an external circuit. A small film capacitor (0.22µF min.),
connected between this pin and GND is recommended to ensure the stability
of the generator and to prevent noise from affecting the reference.
5/22

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L6382D arduino
L6382D
5 Typical electrical performance
Typical electrical performance
Figure 3. UVLO thresholds [V] vs. TJ Figure 4. VCC zener voltage [V] vs. TJ
15
14
13 Vcc(on)
12
11
10
9 Vcc(off)
21
20
19
18
17
16
8 15
7 14
-40 -25 0 25 50 75 100 125 -40 -25 0 25 50 75 100 125
Figure 5. VREF [V] vs. TJ
3.5
3.45
3.4
3.35
3.3
3.25
3.2
3.15
3.1
-40 -25 0 25 50 75
Figure 6. Overcurrent protection
threshold [V] vs. TJ
600
580
560
540
520
500
100 125
-40 -25
0
25 50 75 100 125
Figure 7. Propagation delays [ns] high Figure 8. Propagation delays [ns] low to
to low vs. TJ
high vs. TJ
300 300
250 250
200 200
150 HS
100
50
LS
PF
150 HS
100
50
LS
PF
0
-40
-25
0
25 50 75 100 125
0
-40
-25
0
25 50 75 100 125
11/22

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