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PDF GTL2107 Data sheet ( Hoja de datos )

Número de pieza GTL2107
Descripción (GTL2008 / GTL2107) 12-Bit GTL to LVTTL Transistor
Fabricantes NXP Semiconductors 
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GTL2008; GTL2107
12-bit GTL to LVTTL translator with power good control and
high-impedance LVTTL and GTL outputs
Rev. 02 — 26 September 2006
Product data sheet
1. General description
The GTL2008/GTL2107 is a customized translator between dual Xeon processors,
Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals.
Functionally and footprint identical to the GTL2007, the GTL2008/GTL2107 LVTTL and
GTL outputs were changed to put them into a high-impedance state when EN1 and EN2
are LOW, with the exception of 11BO because its normal state is LOW, so it is forced
LOW. EN1 and EN2 will remain LOW until VCC is at normal voltage, the other inputs are in
valid states and VREF is at its proper voltage to assure that the outputs will remain
high-impedance through power-up.
Both the GTL2008/GTL2107 and the GTL2007 are derived from the GTL2006. They add
an enable function that disables the error output to the monitoring agent for platforms that
monitor the individual error conditions from each processor. This enable function can be
used so that false error conditions are not passed to the monitoring agent when the
system is unexpectedly powered down. This unexpected power-down could be from a
power supply overload, a CPU thermal trip, or some other event of which the monitoring
agent is unaware.
A typical implementation would be to connect each enable line to the system power good
signal or the individual enables to the VRD power good for each processor.
Typically Xeon processors specify a VTT of 1.1 V to 1.2 V, as well as a nominal Vref of
0.73 V to 0.76 V. To allow for future voltage level changes that may extend Vref to 0.63 of
VTT (minimum of 0.693 V with VTT of 1.1 V) the GTL2008/GTL2107 allows a minimum Vref
of 0.66 V. Characterization results show that there is little DC or AC performance variation
between these levels.
The GTL2008 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency
comparator that is used in dual-processor Xeon applications.
The GTL2107 is the Intel designation for the GTL2008.
2. Features
I Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
I EN1 and EN2 disable error output
I All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are
LOW
I 3.0 V to 3.6 V operation
I LVTTL I/O not 5 V tolerant
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Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
Table 3.
Symbol
6BI
5BI
11BO
EN2
7BO2
7BO1
2BI
1BI
VCC
Pin description …continued
Pin Description
20 data input (GTL)
21 data input (GTL)
22 data output (GTL)
23 enable input (LVTTL)
24 data output (GTL)
25 data output (GTL)
26 data input (GTL)
27 data input (GTL)
28 positive supply voltage
7. Functional description
Refer to Figure 1 “Logic diagram of GTL2008/GTL2107”.
7.1 Function tables
Table 4. GTL input signals
H = HIGH voltage level; L = LOW voltage level.
Input
1BI/2BI/3BI/4BI/9BI
L
H
Output[1]
1AO/2AO/3AO/4AO/9AO
L
H
[1] 1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table 5 and
Table 6.
Table 5. EN1 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN1 1AO and 2AO
L 1BI and 2BI disconnected (high-Z)
H follows BI
5A
5BI disconnected
5BI connected
Table 6. EN2 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN2 3AO and 4AO
L 3BI and 4BI disconnected (high-Z)
H follows BI
6A
6BI disconnected
6BI connected
GTL2008_GTL2107_2
Product data sheet
DataSheet4 U .com
Rev. 02 — 26 September 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
Table 13. Dynamic characteristics …continued
VCC = 3.3 V ± 0.3 V
Symbol Parameter
Conditions
Vref = 0.76 V; VTT = 1.2 V
tPLH LOW-to-HIGH propagation delay
nA to nBI; see Figure 4
9BI to 9AO; see Figure 5
nBI to nA or nAO (open-drain outputs);
see Figure 14
9BI to 10BOn
11A to 11BO; see Figure 10
11BI to 11A; see Figure 9
11BI to 11BO
5BI to 7BO1 or 6BI to 7BO2;
see Figure 7
tPHL HIGH-to-LOW propagation delay nA to nBI; see Figure 4
9BI to 9AO; see Figure 5
nBI to nA or nAO (open-drain outputs);
see Figure 14
9BI to 10BOn
11A to 11BO; see Figure 10
11BI to 11A; see Figure 9
11BI to 11BO
5BI to 7BO1 or 6BI to 7BO2;
see Figure 7
tPLZ LOW to OFF-state propagation EN1 to nAO or EN2 to nAO;
delay
see Figure 8
EN1 to 5A (I/O) or EN2 to 6A (I/O);
see Figure 8
tPZL OFF-state to LOW
propagation delay
EN1 to nAO or EN2 to nAO;
see Figure 8
EN1 to 5A (I/O) or EN2 to 6A (I/O);
see Figure 8
tPHZ HIGH to OFF-state
propagation delay
EN2 to 9AO; see Figure 11
tPZH OFF-state to HIGH
propagation delay
EN2 to 9AO; see Figure 11
Min
1
2
2
2
1
2
2
4
2
2
2
2
1
2
[2] 2
100
1
1
2
2
2
2
Typ[1] Max Unit
48
5.5 10
13 18
ns
ns
ns
6 11
48
7.5 11
8 13
7 12
ns
ns
ns
ns
ns
5.5 10
5.5 10
4 10
ns
ns
ns
6 11 ns
5.5 10
ns
8.5 13
ns
14 21 ns
205 350 ns
3 10 ns
3 7 ns
7 10 ns
7 10 ns
5 10 ns
4 10 ns
[1] All typical values are at VCC = 3.3 V and Tamb = 25 °C.
[2] Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 kpull-up and 21 pF load on 11A has about 23 ns RC rise time.
GTL2008_GTL2107_2
Product data sheet
DataSheet4 U .com
Rev. 02 — 26 September 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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