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PDF OXCF950 Data sheet ( Hoja de datos )
| Número de pieza | OXCF950 | |
| Descripción | Single full-duplex asynchronous channel 128-byte deep transmitter / receiver FIFO | |
| Fabricantes | Oxford Semiconductor | |
| Logotipo |  |
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FEATURES
• Single full-duplex asynchronous channel
• 128-byte deep transmitter / receiver FIFO
• Fully software compatible with industry standard
16C550 type UARTs
• Readable FIFO levels
• System clock up to 60MHz
• Flexible clock prescaler from 1 to 31.875
• 9-bitdata framing as well as 5,6,7 and 8
• Detection of bad data in the receiver FIFO
• Automated in-band flow control using programmable
Xon/Xoff characters
• Transmitter and receiver can be disabled
• Low power CMOS
• 3.3V operation, 5V tolerant I/O
• Extended temperature range –40C to +105C
• Software compatible with OXCF950
• 16C950 mode for local bus applications
• Generic embedded driver compatibility mode
OXCF950 rev B
DATA SHEET V1.0
• Programmable by external MicrowireTM EEPROM
(EEPROM programmed via Oxford Semiconductor
utilities).
• Extremely low power consumption by use of
asynchronous UART core and power down (sleep)
modes
• Range of packages -Ultra small 48 pin TQFP package
or a 48 ball TFBGA.
• Supports all UART types 450 up to 950 (fully
programmable)
• CF+ Compliant (Revision 1.4).
• 16-bit PC Card Compliant (PCMCIA Revision 7.1)
• 8 bit Local Bus interface included for PCMCIA
applications
• 2 Multi-purpose I/O pins which can be configured as
interrupt inputs
DESCRIPTION
The OXCF950 rev B is a low cost asynchronous 16-bit PC
card (henceforth referred to as PCMCIA) or Compact Flash
(henceforth referred to as CF) UART (and Local Bus)
device. Local Bus Selection is performed by use of a
MODE pin. Note that Local Bus mode uses indirect
addressing, which is only supported by PCMCIA.
The 3.3V technology has been specified to operate as low
as 2.7 V to allow an in-line regulator to be used for mixed
3V/5V applications. All the I/Os are 5V tolerant with the
exception of the clock/crystal oscillator input.
The EEPROM interface allows the programming of the
Attribute Memory, UART and Local Configuration Registers
during power up or hard/soft reset. This allows different
card manufacturers to modify the information contained in
the Attribute memory or UART/registers as required, for
example PC-Card ID value.
A number of power -down modes are included to keep
power consumption to a minimum. Such features include
clock division (fully programmable) and sleep modes when
a function of the OXCF950 rev B is not being used.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
The OXCF950 rev B contains a single-channel ultra-high
performance UART offering data rates up to 15Mbps and
128-deep transmitter and receiver FIFOs. Deep FIFOs
reduce CPU overhead and allow utilisation of higher data
rates.
It is software compatible with the widely used industry-
standard 16C550 ty pe devices and compatibles, as well as
other OX16C95x family devices.
In addition to increased performance and FIFO size, the
OXCF950 rev B also provides enhanced features including
improved flow control. Automated software flow control
using Xon/Xoff and automated hardware flow control using
CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow
control and interrupt thresholds are fully programmable and
readable, enabling programmers to fine- tune the
performance of their system. FIFO levels are readable to
facilitate fast driver applications.
The addition of software reset enables recovery from
unforeseen error conditions allowing drivers to restart
gracefully. The OXCF950 rev B supports 9-bit data frames
used in multi-drop industrial protocols. It also offers multiple
© Oxford Semiconductor 2001 .
OXCF950B DATA SHEET REV 1.0 –July 2002
Part No. OXCF950-TQ-B
1 page  
OXFORD SEMICONDUCTOR LTD.
OXCF950 rev B DATA SHEET V 1.0
9.2 2.7V – 3.6V OPERATION.................................................................................................................................................... 58
10 TIMING WAVEFORMS / AC CHARACTERISTICS...........................................................................................59
10.1 MEMORY ACCESS............................................................................................................................................................. 59
10.2 I/O ACCESS........................................................................................................................................................................ 60
11 PACKAGE INFORMATION .......................................................................................................................................62
12 ORDERING INFORMATION......................................................................................................................................64
NOTES............................................................................................................................................................................................ 65
CONTACT DETAILS .................................................................................................................................................................66
DISCLAIMER...............................................................................................................................................................................66
Page 5
5 Page 
OXFORD SEMICONDUCTOR LTD.
OXCF950 rev B DATA SHEET V 1.0
4 CONFIGURATION& OPERATION
4.1 Mode Selection
The OXCF950 has four default modes of operation, as
shown in the table below.
MODE pin
0
1
0
1
EE_DI pin
0
0
‘1’ or to external
EEPROM
‘1’ or to external
EEPROM
Operation
‘Generic’ Normal mode
with 3 address bits
decoded for I/O
16C950 mode
(standard local bus type
UART)
‘Normal’ mode with 4
address bits decoded
for I/O
‘Local Bus’ mode with 4
address bits decoded
for I/O
Table 2: Default Modes of Operation
4.1.1 Generic Mode
Generic Mode is compa tible with PCMCIA and CF host
systems. It is the same as ‘Normal’ mode, except that
when I/O accesses take place, only the bottom 3 bits of the
address range are decoded. Similarly the Card Information
Structure indicates an I/O range of 8 locations. This mode
allows generic drivers to locate the UART on a default 8-
byte boundary. In this mode access to the configuration
registers is performed via paging. Generic mode address
decoding can also be selected by EEPROM configuration.
4.1.2 16C950 Mode
This mode is provided for non PCMCIA/CF applications. In
this mode all the PCMCIA/CF decoding, CIS and EEPROM
sections of the design are bypassed and the CF950 acts as
a local-bus style device. To implement this mode -
REG#, EE_DI should be tied to GND,
OE#, WE#, MODE should be tied to VDD.
The user can use A3 to access configuration registers to
allow control of MIO pins and the clock divider. For most
applications, however, A3, MIO1 and MIO0 should also be
tied to GND.
CE1#, IORD#, IOW# and A[2..0] then become the local bus
chip-select and read, write, address access controls.
IREQ# becomes an active-high interrupt output, and
IOIS16# becomes an active-low interrupt output.
4.1.3 Normal/Local Bus Modes
These modes are identical to the previous CF950 modes of
operation. They are suitable for PCMCIA/CF host systems.
4.2 PCMCIA/CF Operation
PCMCIA and CF host systems allow for hot insertion of
cards.
Once a card has been inserted into a host system, the host
system will configure it. The PCMCIA standard defines two
card detect pins, that allow the host to be notified when a
card is inserted or removed.
By default the device will power up in either Normal or
Local Bus mode, depending on the mode pin (and the
EE_DI pin for ‘Generic’ mode). The difference between
these two modes is given in the following table. Note that
the Local Bus mode is not suitable for CF systems.
Normal Mode (MODE=0)
Address bus is 8 bits wide.
Indirect access is not used.
No external local bus.
Local Bus Mode (MODE=1)
Address bus is 4 bits wide.
Indirect access is used.
External local bus supported.
Table 3: Differences between Normal & Local Bus Mode
The host system will wait for the READY# signal to be
active before reading the Card Information Structure, given
in attribute memory within the device. By reading this tuple
information, the host system is able to identify the device
type and the necessary resources requested by the device.
The host system will then load the device-driver software
according to this information and will configure the IO,
memory and interrupt resources. After determining that the
device is a memory and IO type device the host will enable
it’s IO mode by writing to the device’s Configuration
Options Register in attribute memory space. Device
drivers can then access the functions at the assigned
addresses.
A set of local configuration registers have been provided
that can be used to control the device’s characteristics
(such as interrupt handling) and report internal functional
status. These registers can be accessed in IO space,
utilising the same IO space as the local bus (Local Bus
mode only) and are situated above the UART registers.
These local registers can be set up by device drivers or
from the optional EEPROM. In generic mode, the
Page 11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet OXCF950.PDF ] | |
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