|
|
PDF OX9160 Data sheet ( Hoja de datos )
| Número de pieza | OX9160 | |
| Descripción | PCI Peripheral Bridge | |
| Fabricantes | Oxford Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de OX9160 (archivo pdf) en la parte inferior de esta página. Total 38 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
OX9160
PCI Peripheral Bridge with
EPP Parallel Port & 8/32 bit local bus
FEATURES
• 33MHz, 32-bit target PCI controller.
• Fully PCI 2.2 and PCI Power Management 1.0
compliant.
• 8- or 32-bit pass- through Local bus.
• IEEE1284 parallel port.
• Parallel port supports EPP mode for maximum data
transfer rate to printers, removable drives etc.
• Most operations complete within one PCI frame (no
retries).
• Supports shared interrupts
• 12 multi-purpose I/O pins which can be configured as
interrupt input pins.
• EEPROM interface for optional reconfiguration.
• Local bus operation via I/O or memory mapping.
• Local bus supports Intel or Motorola mode signalling.
• Existing driver support for common I/O solutions.
• On-chip oscillator.
• 5.0V operation.
• Low power CMOS.
• 160 TQFP package.
DESCRIPTION
The OX9160 is a low-cost, general purpose PCI bridge
solution designed to ease the migration to PCI of parallel
port cards and instrumentation devices. It is configurable to
provide either a Local bus interface or a bi-directional
parallel port.
Using the local bus function, legacy devices can be easily
accessed throught the target PCI interface, which is
compliant with version 2.2 of the PCI Bus Specification and
version 1.0 of PCI Power Management Specification. All
reads and writes are completed with a minimum of PCI wait
states, which ensures lower PCI bus occupancy than most
similar PCI bridge solutions.
The local bus can be configured to operate with either 8- or
32-bit data, using either Intel x86 style or Motorola style
signalling.
Alternatively the local bus can be disabled in favour of an
integrated IEEE 1284 EPP parallel port. The parallel port is
an IEEE 1284-compliant host interface, which supports
SPP, PS2 (bidirectional) and EPP modes.
The local Bus function is extremely flexible, allowing the
designer to customize the addressable space, divide it into
chip-select regions, access devices via I/O or memory
space mapping, and adjust the timings of all operations.
The default register values have been selected to support
many standard peripheral chips such as I/O controllers and
other ISA- type devices, however all such parameters can
be overwritten using an optional MicrowireTM serial
EEPROM.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 1999
OX9160 Data Sheet Revision 1.2 – June 2001
Part No. OX9160-TQC33- A
1 page  
OXFORD SEMICONDUCTOR LTD.
3 PIN DESCRIPTIONS
Mode
00 01
11
PCI Interface
139, 140, 141, 143, 144, 145,
148, 149, 152, 154, 155, 156,
159, 160, 1, 2, 14, 15, 16, 19,
20, 23, 24, 26, 28, 29, 32, 33,
34, 36, 37, 38
150, 3, 13, 27
136
4
7
5
6
9
12
11
10
151
134
132
138
Local bus
122 N/A 122
123 N/A 123
102
Dir
P_I/O
P_I
P_I
P_I
P_O
P_I
P_O
P_O
P_I/O
P_O
P_I/O
P_I
P_I
P_OD
P_OD
O
O
O
Name
AD[31:0]
C/BE[3:0]#
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA #
PME#
LBRST
LBRST#
LBDOUT
114-7 N/A 114-7
112 N/A 112
113 N/A 113
105-8
118-21
N/A
N/A
N/A
N/A
76-9,
105-8,
118-21
92-5
98-101
N/A
N/A
N/A
N/A
47-55,
58-61,
66-68,
80-87,
92-95,
98-101
O LBCS[3:0]#
O LBDS[3:0]#
O LBWR#
O LBRDWR#
O LBRD#
Z Hi-Z
O LBA[7:0]
O LBA[12:0]
I/O LBD[7:0]
I/O LBD[31:0]
OX9160
Description
Multiplexed PCI Address/Data bus
PCI Command/Byte enable
PCI system clock
Cycle Frame
Device Select
Initiator ready
Target ready
Target Stop request
Parity
System error
Parity error
Initialization device select
PCI system reset
PCI interrupt
Power management event
Local bus active-high reset
Local bus active-low reset
Local bus data out enable. This pin can be used by external
transceivers; it is high when LBD[7:0] are in output mode and low
when they are in input mode.
Local bus active-low Chip-Select (Intel mode)
Local bus active-low Data-Strobe (Motorola mode)
Local bus active-low write-strobe (Intel mode)
Local bus Read-not- Write control (Motorola mode)
Local bus active-low read-strobe (Intel mode)
Permanent high impedance (Motorola mode)
(8-bit mode) Local bus address signals
(32-bit mode) Local bus address signals
(8-bit mode) Local bus data signals
(32-bit mode) Local bus data signals
Data Sheet Revision 1.22
Page 5
5 Page 
OXFORD SEMICONDUCTOR LTD.
OX9160
Local bus
Chip-Select
(Data-Strobe)
LBCS0# (LBDS0#)
LBCS1# (LBDS1#)
LBCS2# (LBDS2#)
LBCS3# (LBDS3#)
PCI Offset from BAR 1
(Memory space)
Lower Address Upper Limit
000h 3FCh
400h 7FCh
800h BFCh
C00h
FFCh
Table 5: PCI address map for local bus (memory)
Note: The description given for I/O and memory accesses
is for an Intel- type configuration for the Local bus. For
Motorola-type configuration, the chip select pins are
redefined to data strobe pins. In this mode the Local bus
offers up to 8 address lines and four data-strobe pins.
4.3.2 PCI access to 32-bit local bus
Access to the Local bus in 32-bit mode is similar to 8-bit
mode (see section 4.3.1) with the following exceptions:
• The local Bus offers a 32-bit bi-directional data bus
and 12 bit address bus
• The PCI address signals ‘AD[13:2]’ are asserted on
LBA[11:0]
• Block size in memory space is programmable by
LT2[28:27] (see section 1.1)
• The Lower-Address-CS-Decode (LT2[26:23])
parameter is used to decode up to 4 chip selects
The block size allocation for chip-select regions is defined
in Table 6.
Number
of Chip
selects
1
2
4
1
2
4
Memory
block size
(Kbytes)
16
16
16
4
4
4
LT2[28:27] LT2[26:23]
‘01’ ‘1010’
‘01’ ‘1001’
‘01’ ‘1000’
‘00’ ‘1000’
‘00’ ‘0111’
‘00’ ‘0110’
Table 6: PCI access to 32-bit local bus (memory)
4.3.3 PCI access to parallel port
When the parallel port is enabled (Mode 01), access to the
port works via BAR definitions as usual, except that there
are two I/O BARs corresponding to two sets of registers
defined to operate a bi-directional Parallel Port. Memory
mapped access to the parallel port is not supported.
The user can change the I/O space block size of BAR0 by
over-writing the default values in LT2[25:20] using the
serial EEPROM (see section 1.1). For example the user
can reduce the allocated space for BAR0 to 4-bytes by
setting LT2[22:20] to ‘001’. The I/O block size allocated to
BAR1 is fixed at 8-Bytes.
Legacy PC parallel ports expect the upper register set to
be mapped 0x400 above the base block, therefore if the
BARs are fixed with this relationship, generic parallel port
drivers can be used to operate the device in all modes.
Example: BAR0 = 0x00000379 (8 bytes at address 0x378)
BAR1 = 0x00000779 (8 bytes at address 0x778)
If this relationship is not used, custom drivers will be
needed.
Data Sheet Revision 1.22
Page 11
11 Page | ||
| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet OX9160.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| OX9160 | PCI Peripheral Bridge | Oxford Semiconductor |
| OX9162 | Integrated Parallel Port/Local Bus and PCI interface | Oxford Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |