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PDF OX16PCI958 Data sheet ( Hoja de datos )

Número de pieza OX16PCI958
Descripción Octal UART
Fabricantes Oxford Semiconductor 
Logotipo Oxford Semiconductor Logotipo



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FEATURES
OX16PCI958 DATA SHEET
Octal UART
with PCI Interface
Efficient 32-bit, 331/3 MHz multi-function, target-only
PCI controller, compliant to PCI Local Bus
Specification 3.0 & PCI Power Management
Specification 1.1
Eight UARTs fully software compatible with 16C550-
type devices
Compatible with existing 16C550/450 device drivers
PCI 2.1, 2.2, 2.3 & 3.0 compliant
Supports both 5.0-V & 3.3-V PCI signalling
32-byte deep FIFO per transmitter & receiver
Baud rates up to 4.125 Mega-baud (using a
16.5 MHz input clock).
Clock can be provided from crystal oscillator or
external clock source
Automated out-of-band flow control using
CTS#/RTS#
Configuration data is held in a small, low-cost serial
MicrowireTM compatible EEPROM
Driver-facilitated DSR/DTR & Xon/Xoff handshaking
5-,6-,7- & 8-bit data framing
1, 1.5 or 2 stop bits
UART enhancements:
Clock prescaler allows more baud rate options
Readable FIFO levels & tuneable trigger levels
improve device driver performance
Programmable “synchronization factor” allows
baud rates up to fclock/4
Extensions to standard register set are
implemented in a safe, easy-to-use way
Low-power design with separate power management
control
Operating temp. range : 0oC—70oC
160-pin QFP package
Operation via IO or memory mapping
Support for multiple wake-up events
DESCRIPTION
The OX16PCI958 contains eight UARTs (Universal
Asynchronous Receiver-Transmitters) and a host
interface suitable for direct connection to a PCI bus.
Once installed and configured by the host OS, it provides
an eight-byte programming interface to each UART. The
UARTs are fully software-compatible with 16C550
devices. The device can be configured to fit the
requirements of RS232 or RS422 applications.
The UARTs convert between RS232-format serial data
on separate transmit and receive lines, and byte-wide I/O
writes and reads on the host interface. Malformed
incoming serial data is flagged along with the data in the
receive FIFO. The state of the UART can be found at
any time by reading status registers, and modem control
(handshaking output) lines can be individually controlled.
Although polled-mode operation is possible, the UART
will usually be operated on a host-interrupt basis. The
interrupt system is designed to allow efficient handling of
interrupt service requests from the UART, for example by
using the prioritised interrupt identification register,
readable FIFO levels, and tuneable FIFO trigger levels.
The internal transmitter and receiver logic runs at a
programmable synchronisation factor of 4x, 8x, or 16x
the serial baud rate. This internal clock is generated by
dividing a reference clock by an integer divisor from 1 to
(216–1). In this way the UART can accommodate a serial
rate of up to 4 125 000 baud (using a 16.5 MHz input
clock).
The OX16PCI958 provides a host interface that can be
directly connected to a PCI bus. It responds to
configuration accesses, and once configured it also
responds to I/O and memory accesses for control of the
UART. The data for configuration space is read from a
small external serial EEPROM at start-up, together with
information on how the OX16PCI958 should be set up.
Oxford Semiconductor Ltd.
External—Free Release
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
Oxford Semiconductor 2005
OX16PCI958 DS-0022—Nov 2005
Part No. OX16PCI958—PQAG

1 page




OX16PCI958 pdf
OXFORD SEMICONDUCTOR LTD.
OX16PCI958 DATA SHEET
2.2. Pin Descriptions
Table 1 lists the pin allocations, names and describes them.
Name
Pin
PAR
CLK
RST#
FRAME#
IRDY#
22
145
144
13
14
Table 1 Pin Descriptions
Dir
IO
I
I
I
I
Description
PCI bus signals
TRDY#
16
OT
DEVSEL# 17
OT
STOP#
18
OT
PERR#
19
OT
SERR#
21
OT
INTA#
143
OT
PME#
146
OT
IDSEL
160
I
AD[31:0]
148, 149,150, 152, 153, 154, 155, 157, 1, 3, 4, 5, 7, 8, 9, 10,
25, 26, 27, 28, 30, 31, 32, 34, 36, 37, 39, 40, 41, 43, 44, 45 IO
C/BE#3
159
I
C/BE#2
12
I
C/BE#1
23
I
C/BE#0
35
I
Chip configuration
EECS
53
O
EECK
52
O
EEDIO
50
IO
Local clock
XTALI
78
I
XTALO
79
O
Local side
LD_EN
140
O
Power and ground
VSS (GND) 6, 15, 24, 33, 42, 49, 51, 60, 69, 77, 88, 97, 106, 115, 124, 134, 142, 151, 158
VDD (5V) 56, 65, 74, 84, 93, 102, 111, 120, 129, 138
VDDP
2, 11, 20, 29, 38, 46, 47, 141, 147, 156
The VDDP pins provide power to the PCI I/O buffers, and must be connected to the +VI/O pins
on the PCI connector.
Table 2 &
DS-0022 Nov 05
External—Free Release
Page 5

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OX16PCI958 arduino
OXFORD SEMICONDUCTOR LTD.
OX16PCI958 DATA SHEET
3.3. PCI Configuration Space Registers
The PCI interface presents a type 0 configuration register set in configuration space, with the
standard extension for power management. Table 11 summarizes the PCI configuration space
registers.
Table 11 PCI Configuration Space Registers
Address
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
Configuration register
31 24 23 16
Device ID
Status
Class code
BIST
Header type
Base address register 0 (BAR0)
Base address register 1 (BAR1)
Base address register 2 (BAR2)
Base address register 3 (BAR3)
Base address register 4 (BAR4)
Base address register 5 (BAR5)
Cardbus CIS pointer
Subsystem device ID
Expansion ROM base address register
RFU
RFU
Max_lat
Min_gnt
Power management capabilities (PMC)
PM_Data
PMCSR_BSE
15
Vendor ID
Command
8
Latency timer
70
Revision ID
Cache line size
Subsystem vendor ID
Capabilities pointer
Interrupt pin
Interrupt line
Next Ptr (always 0)
Cap_ID (always 0)
PMC Control/Status register (PMCSR)
Device ID Register
This register is read-only via configuration
accesses, and returns the current value of the
DID register (see section 3.4 for details of this
and other PCI set-up registers).
Vendor ID Register
This register is read-only via configuration
accesses, and returns the current value of the
VID register.
Status Register
This register records information on the PCI
interface state, as described in the PCI
specification.
Write 1 to bits 11, 14 and 15 to clear them, all
others are read-only.
Bits Description
15 1—parity error, even if parity error
handling is disabled by bit 6 in the
Command register
14 Set whenever the device asserts SERR#.
13 0
12 0
11 Set whenever the device terminates a
transaction with Target-Abort.
10:9 Device select timing. Target access
timing of the function via the DEVSEL#
output. This device is a medium speed
target device (01b)
80
70
50
41
3 Reflects the interrupt state in the
device/function. INTA# is only asserted
when the Interrupt Disable bit in
Command is 0 & this Interrupt Status bit
is a 1. Setting the Interrupt Disable bit to
a 1 has no effect on the state of this bit.
DS-0022 Nov 05
External—Free Release
Page 11

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