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PDF OX16PCI952 Data sheet ( Hoja de datos )
| Número de pieza | OX16PCI952 | |
| Descripción | Integrated High Performance Dual UARTs | |
| Fabricantes | Oxford Semiconductor | |
| Logotipo |  |
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FEATURES
OX16PCI952 DATA SHEET
Integrated High Performance Dual UARTs,
Parallel Port and 5.0v PCI interface
DS_B008A_00
• Two 16C950 High performance UART channels
• IEEE1284 Compliant SPP/EPP/ECP parallel port
• Multi- function target PCI controller. Fully compliant to
PCI bus specification 2.2 and PCI Power Management
1.0.
• Function access to pre-configure each UART and the
parallel port, prior to handover to generic device
drivers.
• UARTs fully software compatible with 16C550- type
devices.
• Baud rates up to 15Mbps in asynchronous mode and
60Mbps in external 1x clock mode
• 128-byte deep FIFO per transmitter and receiver
• Flexible clock prescaler from 1 to 31.875
• Automated in-band flow control using programmable
Xon/Xoff in both directions
DESCRIPTION
• Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
• Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
• Infra-red (IrDA) receiver and transmitter operation
• 5, 6, 7, 8 and 9-bits data framing
• Global Interrupt Status and readable FIFO levels to
facilitate implementation of efficient device drivers
• Detection of bad data in the receiver FIFO
• 2 multi-purpose IO pins which can be configured as
interrupt inputs or ‘wake-up’ pins (via local registers).
• Auto-detection of a range of optional MicrowireTM
compatible EEPROMs, to reconfigure device.
• Operation via IO or memory mapping.
• 5.0V operation
• 128 pin TQFP package
The OX16PCI952 is a single chip solution for PCI-based
serial and parallel expansion add-in cards. It is a dual
function device, offering IO or memory mapped access to
the two ultra-high performance OX16C950 UARTs and the
bi-directional parallel port. These functions are defined by
Function 0 and Function 1, respectively. Serial port cards
with 2 serial ports and a parallel port can be designed
without redefining any device parameters.
Each UART channel in the OX16PCI952, is the fastest
available PC-compatible UART, offering data rates up to
15Mbps and 128-byte deep transmitter and receiver FIFOs.
The deep FIFOs reduce CPU overhead and allow
utilisation of higher data rates. Each UART channel is
software compatible with the widely used industry-standard
16C550 devices and compatibles, as well as the
OX16C95x family of high performance UARTs. In addition
to increased performance and FIFO size, the UARTs also
provide the full set of OX16C95x enhanced features
including automated in-band flow control, readable FIFO
levels, etc.
The parallel port is an IEEE 1284 compliant SPP, EPP and
ECP parallel port that fully supports the existing Centronics
interface. For legacy applications, the PCI resources have
been arranged so that the parallel port can be located at
standard I/O addresses
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
A set of local registers is available to enhance device driver
efficiency and reduce interrupt latency. Each internal UART
has features such as shadowed FIFO fill levels, an interrupt
source register and Good-Data Status, readable in
consecutive DWORD registers and is visible to logical
function0 in both IO space and memory space. The local
registers also provide additional controls for each UART
and the parallel port, to customise the device for the end-
users application.
The efficient 32-bit, 33MHz target-only interface is
compliant with the PCI bus specification version 2.2 and
version 1.0 of PCI Power Management Specification.
For full flexibility, all the default configuration register
values can be overwritten using an optional MicrowireTM
compatible serial EEPROM.
This EEPROM can also be used to provide function access
to pre-configure each UART into enhanced modes or pre-
configure the parallel port, prior to any PCI configuration
accesses and before control is handed to generic device
drivers.
MicrowireTM is a trade mark of National Semiconductor.
© Oxford Semiconductor 2001
OX16PCI952 Datasheet rev 1.1 – June 2001
Part No. OX16PCI952-TQFP- A
1 page  
OXFORD SEMICONDUCTOR LTD.
OX16PCI952
Power management:
Both functions of the OX16PCI952 comply with the PCI
Power Management Specification 1.0 and the PC98/99
Power Management specifications, by offering the
extended capabilities for Power Management and
supporting the power states D0, D2 and D3. This achieves
significant power savings by allowing device drivers to
power down the PCI functions and disable the UART
channels and the parallel port.
A ‘wake-up’ event (the ‘power management event’) is
requested via the PME# pin from either of the power states
D2 or D3. For the UART channels, this wake-up request is
generated through the UART line RI (for power state D3),
and any modem line and the Serial Data In (for power state
D2). For the parallel port, this wake-up request is
generated through the multi-purpose IO pins, MIO(1:0).
Optional EEPROM:
The OX16PCI952 can be reconfigured from an external
MicrowireTM based EEPROM. However, this is not required
in many applications as default values are provided for
typical applications. Features available via the use of the
EEPROM include redefining device ID’s and vendor/sub-
vendor ID fields in the PCI header space, selectively
enabling/disabling interrupts, powerdown and wakeup
requests, and performing function access to pre-configure
the UARTs and the parallel port.
Multi-function device:
The OX16PCI952 is a multi- function device to enable users
to load individual device drivers for the internal serial ports
and the internal parallel port.
DataSheet Revision 1.1
Page 5
5 Page 
OXFORD SEMICONDUCTOR LTD.
OX16PCI952
Pins Dir1
Multi-purpose & External interrupt pins
59 I/O
Name
MIO 0
60 I/O MIO 1
Description
Multi-purpose I/O 0. Can be driven high or low, or be used to
assert PCI interrupts or power management events (PME).
Multi-purpose I/O 1. Can be driven high or low, or be used to
assert PCI interrupts or power management events (PME).
Microwire EEPROM pins
65
64
62
63
Miscellaneous pins
55
56
Power and ground3
1, 10, 21, 30, 38, 46, 58, 77, 89,
103, 118
9, 11, 19, 20, 22, 29, 37, 45, 53,
54, 57, 61, 67, 76, 82, 92, 93, 102,
112, 116, 119, 128
O EE_CK
O EE_CS
IU EE_DI
O EE_DO
ID TEST
I MODE 0
V VDD
G GND
EEPROM clock signal
EEPROM active-high Chip Select Signal
EEPROM data in
(To be connected to the external EEPROM’s DO pin).
When the optional serial EEPROM is connected, this pin
should be pulled up using an external 1-10k resistor. When
the external EEPROM is not required, this external pull-up is
not necessary as the internal pull-up is sufficient.
EEPROM data out.
(To be connected to the external EEPROM’s DI pin)
TESTPIN.
This must be connected to GND.
MODE selector.
MODE0 = 0. Device operates as a dual function device,
where function 0 is the Dual UARTs and Function 1 is the
parallel port.
MODE0 = 1. Device operates only as a single function
device, where function 0 is the Dual UARTs. Function 1 does
not exist, so the parallel port is not visible2 to PCI accesses.
Device Power
Device Gnd.
Table 2: Pin Descriptions
DataSheet Revision 1.1
Page 11
11 Page | ||
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| PDF Descargar | [ Datasheet OX16PCI952.PDF ] | |
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