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PDF DS3994 Data sheet ( Hoja de datos )
| Número de pieza | DS3994 | |
| Descripción | 4-Channel Cold Cathode Fluorescent Lamp Controller | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Rev 0; 10/06
4-Channel Cold-Cathode
Fluorescent Lamp Controller
General Description
The DS3994 is a 4-channel controller for cold-cathode
fluorescent lamps (CCFLs) that backlight liquid crystal
displays (LCDs) in TV and PC monitor applications. The
DS3994’s features make it suitable for use in even the
largest LCDs, while its low BOM cost makes it ideal for
the entire range of LCD TVs and monitors.
The DS3994 can stagger the lamp bursts from each of
the four channels. This feature allows scanning back-
light schemes for video quality improvement to be
implemented using a single CCFL controller IC, making
it very simple and inexpensive to provide this enhance-
ment. In addition, staggering the bursts from each
channel can be used to minimize current ripple on the
display power supply, which is especially important for
larger LCDs. The relative stagger between each of the
channels is programmable, so this feature can be tai-
lored to the specific application.
The DS3994 uses a push-pull drive architecture but it
can also support full and half bridge drive schemes.
Contact the factory for more details.
LCD Televisions
LCD PC Monitors
Applications
Pin Configurations
TOP VIEW
LOSC 1
A0 2
PSYNC 3
POSC 4
BRIGHT 5
SVM 6
GA1 7
GB1 8
LCM1 9
OVD1 10
GA2 11
GB2 12
LCM2 13
OVD2 14
DS3994
SO-300
28 LSYNC
27 FAULT
26 SCL
25 SDA
24 OVD4
23 LCM4
22 GB4
21 GA4
20 OVD3
19 LCM3
18 GB3
17 GA3
16 VCC
15 GND
Features
o High-Density CCFL Controller for LCD TV and
PC Monitor Backlights
o Programmable Staggered Start for Burst Dimming
on Each Channel
o Strike Frequency Boost Option
o Programmable Strike Time
o Can Be Easily Cascaded
o Minimal External Components
o Analog Brightness Control
o Gate Driver Phasing Minimizes DC Supply Current
Surges
o Per-Channel Lamp Fault Monitoring for Lamp
Open, Lamp Overcurrent, Failure to Strike, and
Overvoltage Conditions
o Accurate (±2%) On-Board Oscillator Lamp
Frequency (20kHz to 80kHz)
o Wide Range On-Board DPWM Burst-Dimming
Oscillator (22.5Hz to 440Hz)
o Can Be Synchronized to External Sources for the
Lamp and DPWM Frequencies
o < 10% to 100% Dimming Range
o Soft-Start Minimizes Audible Transformer Noise
o I2C-Compatible Serial Port and On-Board
Nonvolatile (NV) Memory Allow Device
Customization
o 3-Byte NV User Memory for Storage of Serial
Numbers and Date Codes
o 4.5V to 5.5V Single-Supply Operation
o -40°C to +85°C Temperature Range
o 28-Pin SO (300 mils) Package
Ordering Information
PART
TEMP RANGE
DS3994Z+
-40°C to +85°C
+Denotes lead-free package.
PIN-PACKAGE
28 SO-300
Typical Operating Circuits appear at end of data sheet.
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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4-Channel Cold-Cathode
Fluorescent Lamp Controller
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
10
9
8
DPWM = 100%
7 DPWM = 50%
DPWM = 10%
6
5 SVM < 2V
GATE QC = 3.5nC
4
4.5 4.7 4.9
fLF:OSC = 64kHz
5.1 5.3 5.5
SUPPLY VOLTAGE (V)
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
11.0
10.5 VCC = 5.0V VCC = 5.5V
10.0 VCC = 4.5V
9.5
9.0
8.5
8.0
7.5
7.0
6.5
GATE QC = 3.5nC
6.0
-40.0
22.5
fLF:OSC = 64kHz
DPWM = 100%
85.0
TEMPERATURE (°C)
INTERNAL FREQUENCY CHANGE
vs. TEMPERATURE
1.0
0.8
0.6
0.4
0.2 DPWM FREQUENCY
0.0
-0.2 LAMP FREQUENCY
-0.4
-0.6
-0.8
-1.0
-40.0
22.5
TEMPERATURE (°C)
85.0
TYPICAL OPERATION AT 12V
10µs
5.0V GA
10µs
5.0V GB
10µs
2.0V LCM
10µs
2.0V OVD
TYPICAL OPERATION AT 15V
10µs
5.0V GA
10µs
5.0V GB
10µs
2.0V LCM
10µs
2.0V OVD
TYPICAL OPERATION AT 18V
10µs
5.0V GA
10µs
5.0V GB
10µs
2.0V LCM
10µs
2.0V OVD
TYPICAL STARTUP WITH SVM
5ms
2.0V SVM
5ms
5.0V GB
5ms
2.0V LCM
5ms
1.0V OVD
BURST DIMMING AT 150Hz AND 10%
1ms
5.0V GA
1ms
5.0V GB
1ms
2.0V LCM
1ms
2.0V OVD
_____________________________________________________________________ 5
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4-Channel Cold-Cathode
Fluorescent Lamp Controller
ANALOG DIMMING
CONTROL VOLTAGE
0.5V
OR
0.0V
DPWM
SIGNAL
22.5Hz TO 440Hz
RESISTOR TO SET THE
DIMMING FREQUENCY
RESISTOR-SET DIMMING CLOCK
2.0V
OR
3.3V
BRIGHT
PSYNC (OUTPUT)
POSC
ANALOG DIMMING
CONTROL VOLTAGE
0.5V
OR
0.0V
DPWM
SIGNAL
EXTERNAL
DIMMING CLOCK
22.5Hz TO 440Hz
22.5Hz TO 440Hz
EXTERNAL DIMMING CLOCK
2.0V
OR
3.3V
BRIGHT
PSYNC (OUTPUT)
POSC
Figure 3. DPWM Source Configuration Options
Table 1. BRIGHT Analog Dimming Input Slope and Voltage Range Configuration
CR2.7
0
0
1
1
CR3.0
0
1
0
1
RANGE
0.5 to 2V
0.5 to 2V
0 to 3.3V
0 to 3.3V
SLOPE
Positive
Negative
Positive
Negative
MINIMUM BRIGHTNESS
0.5V
2.0V
0V
3.3V
MAXIMUM BRIGHTNESS
2.0V
0.5V
3.3V
0V
DPWM
SIGNAL
22.5Hz TO 440Hz
BRIGHT
PSYNC (INPUT)
POSC
Figure 4. DPWM Receiver Configuration
To generate the DPWM signal internally, the DS3994
requires a clock (referred to as the dimming clock) to
set the DPWM frequency. The user can supply the dim-
ming clock by setting POSCS = 1 in CR1 and applying
an external 22.5Hz to 440Hz signal at the POSC pin, or
DS3994’s clock can be generated by the DS3994’s
oscillator (set POSCS = 0 in CR1), in which case the
frequency is set by an external resistor at the POSC
pin. These two dimming clock options are shown in
Figure 3. Regardless of whether the dimming clock is
generated internally or sourced externally, the POSCR1
and POSCR2 bits in CR2 must be set to match the
desired dimming clock frequency.
Lamp Dimming Control (DPWM)
When the DPWM signal is generated internally, its duty
cycle (and, thus, the lamp brightness) is controlled by a
user-applied analog voltage at the BRIGHT input. Users
can select a positive or negative slope for the bright
pin’s dimming input as well as the voltage range. If
SLOPE = 0 in CR3, then the slope is positive. This
means that a BRIGHT voltage less than the minimum
voltage causes the DS3994 to operate with the minimum
burst duty cycle, providing the lowest brightness set-
ting, while any voltage greater than the maximum volt-
age causes a 100% burst duty cycle (i.e., lamps always
being driven), which provides the maximum brightness.
For voltages between the minimum voltage and the
maximum voltage, the duty cycle varies linearly between
the minimum and 100%.
The internally generated DPWM signal is available at
the PSYNC I/O pin (set RGSO = 0 in CR1) for sourcing
to other DS3994s, if any, in the circuit. This allows all
DS3994s in the system to be synchronized to the same
DPWM signal. The DS3994 that is generating the
DPWM signal for other DS3994s in the system is
referred to as the DPWM source.
______________________________________________________________________________________________________ 11
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| PDF Descargar | [ Datasheet DS3994.PDF ] | |
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