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PDF IDT74LVC16646A Data sheet ( Hoja de datos )
| Número de pieza | IDT74LVC16646A | |
| Descripción | 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER | |
| Fabricantes | Integrated Device Technology | |
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IDT74LVC16646A
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3V CMOS 16-BIT BUS
TRANSCEIVER/REGISTER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
IDT74LVC16646A
FEATURES:
– Typical tSK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
– Extended commercial range of -40°C to +85°C
– VCC = 3.3V ±0.3V, Normal Range
– VCC = 2.7V to 3.6V, Extended Range
– CMOS power levels (0.4µ W typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVC16646A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVC16646A 16-bit bus transceiver/register is built using advanced
dual metal CMOS technology. This high-speed, low power device is
organized as two independent 8-bit D-type transceivers with 3-state D-type
registers. The control circuitry is organized for multiplexed transmission of
data between the A bus and B bus either directly or from the internal storage
registers. Each 8-bit transceiver/register features direction control (DIR),
over-riding Output Enable control (OE) and Select lines (SAB and SBA) to
select either real-time data or stored data. Separate clock inputs are
provided for A and B port registers. Data on the A or B data bus, or both,
can be stored in the internal registers by the low-to-high transitions at the
appropriate clock pins. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC16646A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Functional Block Diagram
56
1OE
1DIR 1
1CLKBA 55
54
1SBA
2
1CLKAB
3
1SAB
5
1A1
A REG
1D
C1
B REG
1D
C1
2OE
29
2DIR
2CLKBA
28
30
2SBA
2CLKAB
2SAB
31
27
26
52 1B1 2A1 15
A REG
1D
C1
B REG
1D
C1
42 2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
c 1998 Integrated Device Technology, Inc.
1
APRIL 1999
DSC-4488/1
1 page  
IDT74LVC16646A
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
EXTENDEDCOMMERCIALTEMPERATURERANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Parameter
Output HIGH Voltage
Test Conditions(1)
VCC = 2.3V to 3.6V
IOH = – 0.1mA
Min.
VCC – 0.2
Max. Unit
—V
VCC = 2.3V
IOH = – 6mA
2—
VCC = 2.3V
IOH = – 12mA
1.7 —
VCC = 2.7V
2.2 —
VCC = 3.0V
2.4 —
VCC = 3.0V
IOH = – 24mA
2.2 —
VOL Output LOW Voltage
VCC = 2.3V to 3.6V
IOL = 0.1mA
— 0.2 V
VCC = 2.3V
IOL = 6mA
— 0.4
IOL = 12mA
— 0.7
VCC = 2.7V
IOL = 12mA
— 0.4
VCC = 3.0V
IOL = 24mA
— 0.55
NOTE:
LVC Link
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
CPD
CPD
Parameter
Power Dissipation Capacitance per Transceiver Outputs enabled
Power Dissipation Capacitance per Transceiver Outputs disabled
Test Conditions
CL = 0pF, f = 10Mhz
Typical
60
12
Unit
pF
pF
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IDT74LVC16646A.PDF ] | |
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