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PDF DP83849I Data sheet ( Hoja de datos )

Número de pieza DP83849I
Descripción PHYTER DUAL Industrial Temperature
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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August 2006
DP83849I PHYTER® DUAL Industrial Temperature with Flexible Port Switching
Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver
General Description
Features
The number of applications requiring Ethernet Con-
nectivity continues to expand. Along with this
increased market demand is a change in application
requirements. Where single channel Ethernet used to
be sufficient, many applications such as wireless
remote base stations and industrial networking now
require DUAL Port functionality for redundancy or sys-
tem management.
The DP83849I is a highly reliable, feature rich device
perfectly suited for industrial applications enabling
Ethernet on the factory floor. The DP83849I features
two fully independent 10/100 ports for multi-port appli-
cations. NATIONAL’s unique port switching capability
also allows the two ports to be configured to provide
fully integrated range extension, media conversion,
hardware based failover and port monitoring.
The DP83849I provides optimum flexibility in MPU
selection by supporting both MII and RMII interfaces.
In addition this device includes a powerful new diag-
nostics tool to ensure initial network operation and
maintenance.
In addition to the TDR scheme, commonly used for
detecting faults during installation, NATIONAL’s inno-
vative cable diagnostics provides for real time continu-
ous monitoring of the link quality. This allows the
system designer to implement a fault prediction mech-
anism to detect and warn of changing or deteriorating
link conditions.
With the DP83849I, National Semiconductor continues
to build on its Ethernet expertise and leadership posi-
tion by providing a powerful combination of features
and flexibility, easing Ethernet implementation for the
system designer.
Low-power 3.3V, 0.18µm CMOS technology
Low power consumption <600mW Typical
3.3V MAC Interface
Auto-MDIX for 10/100 Mb/s
Energy Detection Mode
Flexible MII Port Assignment
Dynamic Integrity Utility
Dynamic Link Quality Monitoring
TDR based Cable Diagnostic and Cable Length Detection
Optimized Latency for Real Time Ethernet Operation
Reference Clock out
RMII Rev. 1.2 Interface (configurable)
SNI Interface (configurable)
MII Serial Management Interface (MDC and MDIO)
IEEE 802.3u MII
IEEE 802.3u Auto-Negotiation and Parallel Detection
IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE 1149.1 JTAG
Integrated ANSI X3.263 compliant TP-PMD physical sub-layer
with adaptive equalization and Baseline Wander compensation
Programmable LED support for Link, 10 /100 Mb/s Mode, Activ-
ity, Duplex and Collision Detect
Single register access for complete PHY status
10/100 Mb/s packet BIST (Built in Self Test)
80-pin TQFP package (12mm x 12mm)
Applications
Medical Instrumentation
Factory Automation
Motor & Motion Control
Wireless Remote Base Station
General Embedded Applications
System Diagram
MPU/CPU
MII/RMII/SNI
MII/RMII/SNI
Port B
DP83849I
Port A
25 MHz
Clock
Source
Status
LEDs
Typical Application
PHYTER is a registered trademark of National Semiconductor Corporation
© 2006 National Semiconductor Corporation
1
10BASE-T
or
100BASE-TX
10BASE-T
or
100BASE-TX
www.national.com

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7.1.5 Auto-Negotiation Advertisement Register (ANAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) . . . . . . . . . . . . . . . . 59
7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) . . . . . . . . . . . . . . . . . 60
7.1.8 Auto-Negotiate Expansion Register (ANER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.1.10 PHY Status Register (PHYSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.1.11 MII Interrupt Control Register (MICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1.12 MII Interrupt Status and Misc. Control Register (MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1.13 Page Select Register (PAGESEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.2 Extended Registers - Page 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.2.1 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.2.2 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.2.3 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.2.4 RMII and Bypass Register (RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.2.5 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.2.6 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.2.7 10 Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.2.8 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2.9 Phy Control Register 2 (PHYCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2.10 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.3 Link Diagnostics Registers - Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h . . . . . . . . . . . . . . . . . 77
7.3.2 100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h . . . . . . . . . 77
7.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3.4 TDR Window Register (TDR_WIN), Page 2, address 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3.5 TDR Peak Register (TDR_PEAK), Page 2, address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3.6 TDR Threshold Register (TDR_THR), Page 2, address 19h . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah . . . . . . . . . . . . . . . . . . . . . . 80
7.3.8 Variance Data Register (VAR_DATA), Page 2, address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . 80
7.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3.10 Link Quality Data Register (LQDR), Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.1 DC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
8.2 AC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.2.6 100BASE-TX MII Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.2.7 100BASE-TX MII Transmit Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8.2.9 100BASE-TX MII Receive Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.2.10 100BASE-TX MII Receive Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.2.13 10 Mb/s Serial Mode Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.2.14 10 Mb/s Serial Mode Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.2.15 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.2.16 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.2.17 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.2.18 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.2.19 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.2.20 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.2.21 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.2.23 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.2.24 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.2.25 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.2.26 RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.2.27 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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1.2 MAC Data Interface (Continued)
Signal Name
RX_CLK_A
RX_CLK_B
RX_DV_A
RX_DV_B
RX_ER_A
RX_ER_B
RXD[3:0]_A
RXD[3:0]_B
CRS_A/CRS_DV_A
CRS_B/CRS_DV_B
COL_A
COL_B
Type
O
O
O
O
O
O
Pin #
Description
79 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive
63 clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input
as the 50 MHz reference for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive
clocks for 10 Mb/s SNI mode.
80 MII RECEIVE DATA VALID: Asserted high to indicate that valid data
62 is present on the corresponding RXD[3:0].
RMII RECEIVE DATA VALID: Asserted high to indicate that valid
data is present on the corresponding RXD[1:0]. This signal is not re-
quired in RMII mode, since CRS_DV includes the RX_DV signal, but
is provided to allow simpler recovery of the Receive data.
This pin is not used in SNI mode.
2 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to
60
indicate that an invalid symbol has been detected within a received
packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenev-
er an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s
mode. This pin is also asserted on detection of a False Carrier event.
This pin is not required to be used by a MAC in RMII mode, since the
Phy is required to corrupt data on a receive error.
This pin is not used in SNI mode.
9,8,5,4 MII RECEIVE DATA: Nibble wide receive data signals driven syn-
53,56,57,58 chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for
10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is
asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven
synchronously to the X1 clock, 50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchro-
nously to the RX_CLK. RXD_0 contains valid data when CRS is as-
serted. RXD[3:1] are not used in this mode.
1 MII CARRIER SENSE: Asserted high to indicate the receive medium
61 is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal com-
bines the RMII Carrier and Receive Data Valid indications. For a de-
tailed description of this signal, see the RMII Specification.
SNI CARRIER SENSE: Asserted high to indicate the receive medium
is non-idle. It is used to frame valid receive data on the RXD_0 signal.
3 MII COLLISION DETECT: Asserted high to indicate detection of a
59
collision condition (simultaneous transmit and receive activity) in 10
Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin
is also asserted for a duration of approximately 1µs at the end of
transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is
always logic 0. There is no heartbeat function during 10 Mb/s full du-
plex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL sig-
nal is required. The MAC will recover CRS from the CRS_DV signal
and use that along with its TX_EN signal to determine collision.
SNI COLLISION DETECT: Asserted high to indicate detection of a
collision condition (simultaneous transmit and receive activity) in 10
Mb/s SNI mode.
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