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PDF WM8200 Data sheet ( Hoja de datos )

Número de pieza WM8200
Descripción 40MSPS ADC
Fabricantes Wolfson Microelectronics 
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WM8200-10/12
40MSPS ADC with PGA
DESCRIPTION
The WM8200 is a CMOS high speed, low power, pipeline
analogue-to-digital converter (ADC) with 10 or 12-bit output
options. It also has an on-chip programmable gain amplifier
(PGA), dc clamp circuit and internal voltage references.
Conversion is controlled by a single clock input.
The device has a high bandwidth differential sample and hold
input, which gives excellent common-mode noise immunity
and low distortion. Alternatively, it can be driven in single
ended fashion with an optional voltage clamp for dc
restoration that can take its reference from an on-chip 10-bit
DAC.
The WM8200 provides internal reference voltages for setting
the ADC full-scale range without the requirement for external
circuitry. However, it can also accept external references for
applications where shared or high-precision references are
required.
A 3-wire serial interface is used to control the device and a
10 or 12-bit parallel interface is to read ADC conversion data.
ADC data can be output in unsigned binary or two’s
complement format.
The WM8200 operates with a single 3V supply and is
supplied in a 28-lead QFN package.
BLOCK DIAGRAM
CLAMP
FEATURES
10 or 12-bit resolution ADC
40MSPS conversion rate
Programmable Gain Amplifier (PGA)
Adjustable internal voltage references
Built in clamp function (dc restore) with 10-bit DAC
Wide Input Bandwidth - 900MHz
Unsigned Binary or Two’s complement output format
Programmable via 3-wire serial MPU interface
Single 3V supply operation
Low power - 100mW typical at 3.0V supplies
Powerdown mode to <0.1mW typical
28 lead QFN package
APPLICATIONS
Digital Still Cameras
Composite Video Digitisation
Digital Copiers
Digital Video Cameras
CLAMP
AMPLIFIER
CLAMP
LEVEL
DAC
CONTROL
REGISTERS
SCLK
SDIN
CSB
AINP
AINN
S/H
PGA
AADDCC
CCOoRreE
OUTPUT
BUFFERS
DO[9:0] WM8200-10
or
DO[11:0] WM8200-12
REFSENSE
VREF
MODE
ON-CHIP
REFERENCE
GENERATOR
AVDD AGND
REFB REFT
TIMING
CONTROL
WM8200
CLK
DVDD
DGND
WOLFSON MICROELECTRONICS LTD
www.wolfsonmicro.com
Product Preview March 2002, Rev 1.22
Copyright 2002 Wolfson Microelectronics Ltd.

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WM8200
Product Preview
ELECTRICAL CHARACTERISTICS
Test Conditions:
AVDD = DVDD = 3.0V, fCLK = 40MHz, 50% duty cycle, MODE = AVDD, VREF=1.0V (REFT = 2.0V, REFB = 1.0V),
PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated.
PARAMETER
SYMBOL
DC Accuracy
Integral nonlinearity
INL
Differential nonlinearity
DNL
Offset error
Full scale error
Missing codes
Analogue Input Signal to AIN pins
Differential analogue input
voltage (AINP-AINN)
Switched input capacitance
Conversion Characteristics
Conversion frequency
fCLK
TEST CONDITIONS
PGA=1x gain
Pipeline delay
Dynamic Performance (differential input mode)
Effective number of bits
ENOB
fIN = 4.8MHz
fIN = 20MHz
Spurious free dynamic range
SFDR
fIN = 4.8MHz
fIN = 20MHz
Total harmonic distortion
THD
fIN = 4.8MHz
fIN = 20MHz
Signal to noise ratio
SNR
fIN = 4.8MHz
fIN = 20MHz
Signal to noise and distortion
ratio
PGA
SINAD
fIN = 4.8MHz
fIN = 20MHz
Gain range (linear scale)
Gain step size (linear scale)
Clamp
Clamp DAC resolution
Clamp DAC output voltage
Clamp DAC DNL
Clamp output voltage error
REFB, REFT internal ADC reference voltage outputs (MODE= AVDD)
Reference voltage top, REFT
VREF = 0.5V
(AVDD=3V)
VREF= 1.0V
Reference voltage bottom,
REFB (AVDD=3V)
VREF = 0.5V
VREF= 1.0V
VREF Input / Output specifications (ADC Input Range = VREFx2)
Internal 0.5V reference to VREF
REFSENSE = VREF
Internal 1V reference to VREF
REFSENSE = AGND
External reference applied to
VREF pin
REFSENSE = AVDD
Input impedance in internal ADC
reference mode
REFSENSE = AVDD,
MODE = AVDD
MIN
TYP
MAX
UNIT
±1.0 LSB
±0.3 LSB
0.7 % of FSR
2.2 % of FSR
No missing codes guaranteed
-1
5
0.5
REFB
-40
0.5
1.2
4
9.6
9.5
72
70
-72.5
-71.6
60
57
59.7
59.6
0.5
10
±1
1.75
2
1.25
1
0.5
1
14
1V
pF
40 MHz
cycles of
CLK
bits
dB
dB
dB
dB
4
REFT
40
V/V
V/V
bits
V
LSB
mV
V
V
1V
k
w
PP Rev 1.22 March 2002
5

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WM8200 arduino
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WM8200
Product Preview
CONTROL INTERFACE
The internal control registers are programmable via the 3-wire serial interface. SDIN is used for the
program data, SCLK is used to clock in the data and CSB is used to latch in the program data. The
3-wire interface protocol is shown in Figure 6.
CSB
SCLK
SDIN
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS
Figure 6: 3-Wire Serial Interface
DATA
1. A[3:0] are Control Address Bits
2. D[7:0] are Control Data Bits
3. CSB is edge sensitive – the data is latched on the rising edge of CSB.
REGISTER MAP
Table 3 shows the location of each control bit used to determine the operation of the WM8200. The
procedure for programming the register map is described in the CONTROL INTERFACE section.
ADDR
NAME
DEFAULT
(HEX)
0000
0001
0010
0011
0100 -
1111
Clamp Reg 1
Clamp Reg 2
PGA Control
Control
Reserved
00
00
01
00
00
Table 3: Register Map
B7
DAC[7]
0
0
0
B6
DAC[6]
0
0
0
B5
DAC[5]
0
PGASENSE
0
BIT
B4 B3 B2
DAC[4]
0
DAC[3] DAC[2]
00
PGAOFF
0 PGA[2]
CLPSEL OEB TWOSC
B1
DAC[1]
DAC[9]
PGA[1]
CLDIS
B0
DAC[0]
DAC[8]
PGA[0]
PD
Reserved, do not write to these register locations
w
PP Rev 1.22 March 2002
11

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