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PDF 93AA86A Data sheet ( Hoja de datos )

Número de pieza 93AA86A
Descripción 16K Microwire Compatible Serial EEPROM
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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93AA86A/B/C, 93LC86A/B/C,
93C86A/B/C
16K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number VCC Range
93AA86A
93AA86B
93LC86A
93LC86B
93C86A
93C86B
93AA86C
93LC86C
93C86C
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
1.8-5.5
2.5-5.5
4.5-5.5
ORG Pin
No
No
No
No
No
No
Yes
Yes
Yes
PE Pin
No
No
No
No
No
No
Yes
Yes
Yes
Features:
• Low-power CMOS technology
• ORG pin to select word size for ‘86C’ version
• 2048 x 8-bit organization ‘A’ devices (no ORG)
• 1024 x 16-bit organization ‘B’ devices (no ORG)
• Program Enable pin to write-protect the entire
array (‘86C’ version only)
• Self-timed erase/write cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential read function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Temperature ranges supported:
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Pin Function Table
Name
Function
CS
CLK
DI
DO
VSS
PE
ORG
VCC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Program Enable
Memory Configuration
Power Supply
Word Size
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
8 or 16-bit
8 or 16-bit
8 or 16-bit
Temp Ranges
I
I
I, E
I, E
I, E
I, E
I
I, E
I, E
Packages
OT
OT
OT
OT
OT
OT
P, SN, ST, MS, MC
P, SN, ST, MS, MC
P, SN, ST, MS, MC
Description:
The Microchip Technology Inc. 93XX86A/B/C devices
are 16K bit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93XX86C are dependent upon external logic
levels driving the ORG pin to set word size. In the
SOT-23 package, the 93XX86A devices provide
dedicated 8-bit memory organization, while the
93XX86B devices provide dedicated 16-bit memory
organization. A Program Enable (PE) pin allows the
user to write-protect the entire memory array.
Advanced CMOS technology makes these devices
ideal for low-power, nonvolatile memory applications.
The entire 93XX Series is available in standard
packages including 8-lead PDIP and SOIC, and
advanced packaging including 8-lead MSOP, 6-lead
SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. Pb-free
(Pure Matte Sn) finish is available.
Package Types (not to scale)
PDIP/SOIC
(P, SN)
SOT-23
(OT)
CS
CLK
DI
DO
1
2
3
4
8 VCC
7 PE
6 ORG
5 VSS
DO 1
VSS 2
DI 3
6 VCC
5 CS
4 CLK
TSSOP/MSOP
(ST, MS)
CS
CLK
DI
DO
1
2
3
4
8 VCC
7 PE
6 ORG
5 VSS
CS 1
CLK 2
DI 3
DO 4
DFN
(MC)
8 VCC
7 PE
6 ORG
5 VSS
© 2005 Microchip Technology Inc.
DataSheet4 U .com
DS21797G-page 1

1 page




93AA86A pdf
www.DataSheet4U.com
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.0 FUNCTIONAL DESCRIPTION
When the ORG pin (93XX86C) is connected to VCC,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy status during a programming operation. The
Ready/Busy status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1 Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be
connected between DI and DO.
2.3 Data Protection
All modes of operation are inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an EWDS
command should be performed after
every write operation and an external 10
kΩ pull-down protection resistor should be
added to the CS pin.
After power-up the device is automatically in the EWDS
mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Note:
To prevent accidental writes to the array in
the 93XX86C devices, set the PE pin to a
logic low.
© 2005 Microchip Technology Inc.
DataSheet4 U .com
DS21797G-page 5

5 Page





93AA86A arduino
www.DataSheet4U.com
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The self-timed auto-erase and programming cycle is
initiated by the rising edge of CLK on the last data bit.
Clocking of the CLK pin is not necessary after the
device has entered the WRAL cycle. The WRAL
command does include an automatic ERAL cycle for
the device. Therefore, the WRAL instruction does not
require an ERAL instruction, but the chip must be in the
EWEN status.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be 4.5V for proper operation of WRAL.
FIGURE 2-7:
CS
CLK
WRAL TIMING
TCSL
DI 1 0 0 0 1 x ••• x Dx ••• D0
TSV TCZ
DO High-Z
Busy Ready
High-Z
TWL
© 2005 Microchip Technology Inc.
DataSheet4 U .com
DS21797G-page 11

11 Page







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