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PDF T14L1024A Data sheet ( Hoja de datos )
| Número de pieza | T14L1024A | |
| Descripción | 128K X 8 HIGH SPEED CMOS STATIC RAM | |
| Fabricantes | Taiwan Memory Technology | |
| Logotipo |  |
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tm TE
CH
SRAM
Preliminary T14L1024A
128K X 8 HIGH SPEED
CMOS STATIC RAM
FEATURES
• Fast Address Access Times : 10/12/15ns
• Single 3.3V ±0.3V power supply
• Low Power Consumption : 110/105/100mA
• TTL I/O compatible
• 2.0V data retention mode
• Automatic power-down when deselected
• Available packages :
32-pin 300 mil DIP/SOJ & 32-pin SOP/TSOP-I
• Industry Standard Pin Assignment
PIN CONFIGURATION
NC
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIP
/
SOJ
/
SOP
32 Vcc
31 A11
30 CE2
29 WE
28 A12
27 A13
26 A14
25 A15
24 OE
23 A16
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A15
A14
A13
A12
WE
CE2
A11
VCC
NC
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP-I
32 OE
31 A16
30 CE1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 VSS
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
GENERAL DESCRIPTION
The T14L1024A is a one-megabit density, fast
static random access memory organized as 131,072
words by 8 bits. It is designed for use in high
performance memory applications such as main
memory storage and high speed communication
buffers. Fabricated using high performance CMOS
technology, access times down to 10ns are achieved.
Memory expansion by banking is easily
accomplished using the chip enable pins CE1 and
CE2. This device is packaged in a standard 32-pin
300 mil DIP/SOJ and 32-pin SOP/TSOP-I.
BLOCK DIAGRAM
Vcc
Vss
A0
...
DECODER
.
A16
CORE
ARRAY
CE1
CE2
WE
OE
DATA I/O
I/O0
..
.
I/O7
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O0 - I/O7
/CE1,CE2
/WE
/OE
Vcc
Vss
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable
Output Enable
Power Supply
Ground
PART NUMBER EXAMPLES
PACKAGE
SPEED
T14L1024A-10J SOJ 300mil
10ns
T14L1024A-10P TSOP-I 8x13.4mm 10ns
T14L1024A-10H TSOP-I 8x20mm 10ns
T14L1024A-10N DIP 300mil
10ns
T14L1024A-10D SOP
10ns
TM Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: SEP. 2002
Revision:0.F
DataSheet4 U .com
1 page  
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tm TE
CH
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
Address
Dout
tAA
tOH
t
RC
READ CYCLE 2
(Chip Enable Controlled)
tRC
Address
t
AA
OE
CE1
t
AOE
t
O LZ
CE2
D
out
t
ACS
tCLZ
Preliminary T14L1024A
tOH
tOH
t
OHZ
tCH Z
DON'T CARE
UNDEFINED
TM Technology, Inc. reserves the right
P. 5
to change products or specifications without notice.
DataSheet4 U .com
Publication Date: SEP. 2002
Revision:0.F
5 Page 
www.DataSheet4U.com
tm TE
CH
PACKAGE DIMENSIONS
32-LEAD DIP (300 mil)
A
32
Preliminary T14L1024A
17
A1
1
B4
B
B1
C2 C1 C
16
B2
B3
0
D
D1
Symbol
A
A1
B
B1
B2
B3
B4
C
C1
C2
D
D1
θ
Dimension in mm
Min Nom Max
-
40.64
41.15
7.26 7.36 7.46
- - 5.08
3.05 3.30 3.56
3.68 3.81 3.94
0.38 -
-
- - 1.65
2.29 2.54 2.79
0.41 0.46 0.56
1.47 1.52 1.63
7.49 8.00 8.50
10.92
11.43
11.94
0° - 15°
Dimension in inch
Min Nom Max
- 1.60 1.62
0.286
0.290
0.294
- - 0.200
0.120
0.130
0.140
0.145
0.150
0.155
0.015
-
-
- - 0.065
0.090
0.100
0.110
0.016
0.018
0.022
0.58 0.60 0.64
0.295
0.315
0.335
0.430
0.450
0.470
0° - 15°
TM Technology, Inc. reserves the right
P. 11
to change products or specifications without notice.
Publication Date: SEP. 2002
Revision:0.F
DataSheet4 U .com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet T14L1024A.PDF ] | |
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