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PDF IDT74ALVCH16501 Data sheet ( Hoja de datos )

Número de pieza IDT74ALVCH16501
Descripción 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDT74ALVCH16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
3.3V CMOS 18-BIT UNIVERSAL
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
IDT74ALVCH16501
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB
is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/
flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs
are active. When OEAB is low, the outputs are in the high-impedance state.
DataflowforBtoAissimiliartothatofAtoBbutusesOEBA,LEBA,andCLKBA.
The output enables are complementary (OEAB is active high and OEBA is active
low).
The ALVCH16501 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16501 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB 1
CLKAB 55
LEAB 2
LEBA 28
CLKBA 30
OEBA 27
A1 3
1D
C1
CLK
1D
C1
CLK
54
B1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
DataSheet4 U .com
1
JANUARY 2004
DSC-4738/2

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IDT74ALVCH16501 pdf
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IDT74ALVCH16501
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Symbol Parameter
Min. Max.
fMAX 150 —
tPLH PropagationDelay
1 4.8
tPHL Ax to Bx or Bx to Ax
tPLH PropagationDelay
1.1 5.7
tPHL LE to Ax or Bx
tPLH PropagationDelay
1.2 6.1
tPHL CLK to Ax or Bx
tPZH OutputEnableTime
1.3 6.3
tPZL OEBA to Ax
tPZH OutputEnableTime
1 5.8
tPZL OEAB to Bx
tPHZ OutputDisableTime
1.3 5.3
tPLZ OEBA to Ax
tPHZ OutputDisableTime
1.5 6.2
tPLZ OEAB to Bx
tSU Set-up Time, data before CLK
2.2 —
tSU Set-up Time, data before LE
CLK LOW
1.9 —
CLK HIGH
1.3 —
tH Hold Time, data after CLK
0.6 —
tH Hold Time, data after LE, CLK HIGH or LOW
1.4 —
tW Pulse Width, LE HIGH
3.3 —
tW Pulse Width, CLK HIGH or LOW
3.3 —
tSK(o) Output Skew(2)
——
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIALTEMPERATURERANGE
VCC = 2.7V
Min. Max.
150 —
— 4.5
VCC = 3.3V ± 0.3V
Min. Max.
150 —
1 3.9
Unit
MHz
ns
— 5.3 1.3 4.6 ns
— 5.6 1.4 4.9 ns
— 6 1.1 5 ns
— 5.3
1 4.6 ns
— 4.6 1.3 4.2 ns
— 5.7 1.4 5 ns
2.1 — 1.7 — ns
1.6 — 1.5 — ns
1.1 —
1—
0.6 — 0.7 — ns
1.7 — 1.4 — ns
3.3 — 3.3 — ns
3.3 — 3.3 — ns
— — — 500 ps
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