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PDF IDT2308A Data sheet ( Hoja de datos )
| Número de pieza | IDT2308A | |
| Descripción | 3.3V ZERO DELAY CLOCK MULTIPLIER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
MULTIPLIER
IDT2308A
FEATURES:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT2308A-1 1x
– IDT2308A-2 1x, 2x
– IDT2308A-3 2x, 4x
– IDT2308A-4 2x
– IDT2308A-1H and -2H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
DESCRIPTION:
The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308A has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT2308A enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than25µA
for Industrial temperature range, and the outputs are tri-stated.
The IDT2308A is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT2308A is characterized for both Industrial and Commercial opera-
tion.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
16
FBK
2
1
REF
PLL
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
S2 8
S1 9
Control
Logic
(-2, -3) 2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2004 Integrated Device Technology, Inc.
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TEMPERATURE
1
RANGES
JULY 2004
DSC 6587/8
1 page  
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IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS - COMMERCIAL
Symbol Parameter
Conditions
t1 OutputFrequency
30pF Load, all devices
t1 OutputFrequency
20pF Load, -1H, -2H Devices
t1 OutputFrequency
15pF Load, -1, -2, -3, -4 devices
Duty Cycle = t2 ÷ t1
(-1, -2, -3, -4, -1H, -2H)
Measured at 1.4V, FOUT = 66.66MHz
30pF Load
Duty Cycle = t2 ÷ t1
(-1, -2, -3, -4, -1H, -2H)
Measured at 1.4V, FOUT = 50MHz
15pF Load
t3 Rise Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 30pF Load
t3 Rise Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 15pF Load
t3 Rise Time (-1H, -2H)
Measured between 0.8V and 2V, 30pF Load
t4 Fall Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 30pF Load
t4 Fall Time (-1, -2, -3, -4)
Measured between 0.8V and 2V, 15pF Load
t4 Fall Time (-1H)
Measured between 0.8V and 2V, 30pF Load
t5 Output to Output Skew on same Bank
All outputs equally loaded
(-1, -2, -3, -4)
Output to Output Skew (-1H, -2H)
All outputs equally loaded
Output Bank A to Output Bank B (-1, -4, -2H)
All outputs equally loaded
Output Bank A to Output Bank B Skew (-2, -3)
All outputs equally loaded
t6 Delay, REF Rising Edge to FBK Rising Edge
Measured at VDD/2
t7 Device to Device Skew
Measured at VDD/2 on the FBK pins of devices
t8 Output Slew Rate
Measured between 0.8V and 2V on -1H, -2H
device using Test Circuit 2
tJ Cycle to Cycle Jitter
(-1, -1H, -4)
Measured at 66.67 MHz, loaded outputs, 15pF Load
Measured at 66.67 MHz, loaded outputs, 30pF Load
Measured at 133.3 MHz, loaded outputs, 15pF Load
tJ Cycle to Cycle Jitter
Measured at 66.67 MHz, loaded outputs, 30pF Load
(-2, -2H, -3)
Measured at 66.67 MHz, loaded outputs, 15pF Load
tLOCK PLL Lock Time
Stable Power Supply, valid clocks presented
on REF and FBK pins
Min. Typ. Max. Unit
10 — 100 MHz
10 — 133.3 MHz
10 — 133.3 MHz
40 50 60 %
45 50 55 %
— — 2.2 ns
— — 1.5 ns
— — 1.5 ns
— — 2.2 ns
— — 1.5 ns
— — 1.25 ns
— — 200 ps
— — 200 ps
— — 200 ps
— — 400 ps
— 0 ±250 ps
— 0 700 ps
1 — — V/ns
— — 200
— — 200 ps
— — 100
— — 400 ps
— — 400
— — 1 ms
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