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PDF ICS9DB401 Data sheet ( Hoja de datos )
| Número de pieza | ICS9DB401 | |
| Descripción | Four Output Differential Buffer | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
Four Output Differential Buffer for PCI Express
ICS9DB401
Recommended Application:
DB800 Version 2.0 Yellow Cover part with PCI Express
support with extended bypass mode frequency range.
Output Features:
• 4 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
Key Specifications:
• Outputs cycle-cycle jitter: < 50ps
• Outputs skew: < 50ps
• Extended frequency range in bypass mode:
Revision B: up to 333.33MHz
Revision C: up to 400MHz
Features/Benefits:
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
• Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Pin Configurations
VDD 1
SRC_IN 2
SRC_IN# 3
GND 4
VDD 5
DIF_1 6
DIF_1# 7
OE_1 8
DIF_2 9
DIF_2# 10
VDD 11
BYPASS#/PLL 12
SCLK 13
SDATA 14
OE_INV = 0
VDD 1
SRC_IN 2
SRC_IN# 3
GND 4
VDD 5
DIF_1 6
DIF_1# 7
OE1# 8
DIF_2 9
DIF_2# 10
VDD 11
BYPASS#/PLL 12
SCLK 13
SDATA 14
OE_INV = 1
28 VDDA
27 GNDA
26 IREF
25 OE_INV
24 VDD
23 DIF_6
22 DIF_6#
21 OE_6
20 DIF_5
19 DIF_5#
18 VDD
17 HIGH_BW#
16 SRC_STOP#
15 PD#
28 VDDA
27 GNDA
26 IREF
25 OE_INV
24 VDD
23 DIF_6
22 DIF_6#
21 OE6#
20 DIF_5
19 DIF_5#
18 VDD
17 HIGH_BW#
16 SRC_STOP
15 PD
28-pin SSOP & TSSOP
1014B—09/07/06
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Integrated
Circuit
Systems, Inc.
ICS9DB401
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Supply Voltage
VIL Input Low Voltage
VIH Input High Voltage
Ts Storage Temperature
Tambient
Ambient Operating Temp
Tcase
Case Temperature
Input ESD protection
ESD prot
human body model
Min
GND-0.5
-65
0
2000
Max
4.6
4.6
VDD+0.5V
150
70
115
Units
V
V
V
V
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH 3.3 V +/-5% 2
VIL
3.3 V +/-5%
GND - 0.3
IIH
VIN = VDD
-5
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
Operating Supply Current
Powerdown Current
Input Frequency
Input Frequency
Input Frequency
Pin Inductance1
Input Capacitance1
PLL Bandwidth
IDD3.3PLL
IDD3.3ByPass
IDD3.3PD
FiPLL
FiBypass
FiBypass
Lpin
CIN
COUT
BW
Full Active, CL = Full load;
all diff pairs driven
all differential pairs tri-stated
PLL Mode
Bypass Mode (Revision B/REV
ID = 1H)
Bypass Mode (Revision C/REV
ID = 2H)
Logic Inputs
Output pin capacitance
PLL Bandwidth when
PLL_BW=0
PLL Bandwidth when
PLL_BW=1
50
0
0
1.5
2.4
0.7
175
160
3
1
Clk Stabilization1,2
TSTAB
From VDD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
0.5
Modulation Frequency
fMOD
Triangular Modulation
Tdrive_SRC_STOP#
DIF output enable after
SRC_Stop# de-assertion
Tdrive_PD#
DIF output enable after
PD# de-assertion
Tfall
Fall time of PD# and
SRC_STOP#
Trise
Rise time of PD# and
SRC_STOP#
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3Time from deassertion until outputs are >200 mV
30
10
1014B—09/07/06
MAX
VDD + 0.3
0.8
5
UNITS NOTES
V
V
uA
uA
200
175
40
4
200
333.33
400
7
4
4
3.4
1.4
uA
mA
mA
mA
mA
MHz
MHz
MHz
nH
pF
pF
MHz
MHz
1
1
1
1
1
1 ms 1,2
33 kHz 1
15 ns 1,3
300 us 1,3
5 ns 1
5 ns 2
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Integrated
Circuit
Systems, Inc.
ICS9DB401
PD#
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before
shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering
down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending
on the PD# drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PWRDWN#
DIF
DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion.
PWRDWN#
DIF
DIF#
Tstable
<1mS
Tdrive_PwrDwn#
<300uS, >200mV
1014B—09/07/06
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