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PDF ICS9DB306 Data sheet ( Hoja de datos )
| Número de pieza | ICS9DB306 | |
| Descripción | PCI Express / Jitter Attenuator | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS9DB306 is a high performance 1-to-6
ICS Differential-to LVPECL Jitter Attenuator designed
HiPerClockS™ for use in PCI Express™ systems. In some PCI
Express™ systems, such as those found in desktop
PCs, the PCI Express™ clocks are generated from
a low bandwidth, high phase noise PLL frequency
synthesizer. In these systems, a zero delay buffer may be
required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS9DB306 has 2 PLL bandwidth modes. In low
bandwidth mode, the PLL loop BW is about 500kHz and this
setting will attenuate much of the jitter from the reference clock
input while being high enough to pass a triangular input spread
spectrum profile. There is also a high bandwidth mode which
sets the PLL bandwidth at 1MHz which will pass more spread
spectrum modulation.
For serdes which have x30 reference multipliers instead of x25
multipliers, 5 of the 6 PCI Express™ outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by configuring the appropri-
ate frequency select pins (FS0:1). Output PCIEX0 will always
run at the reference clock frequency (usually 100MHz) in desk-
top PC PCI Express™ Applications.
Features
• Six differential LVPECL output pairs
• 1 differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Output skew: 135ps (maximum)
• Cycle-to-Cycle jitter: 25ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
3ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
• Industrial temperature information available upon request
BLOCK DIAGRAM
nOE0
1 Disabled
0 Enabled
CLK
nCLK
Buffer
Phase
Detector
Loop
Filter
VCO
÷5
Internal Feedback
BYPASS
nOE1
1 Disabled
0 Enabled
0
÷5
1
0 ÷4
1 ÷5
FS0
0
1
0 ÷5
1 ÷4
0
1
FS1
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
PCIEXT2
nPCIEXC2
PCIEXT3
nPCIEXC3
PCIEXT4
nPCIEXC4
PCIEXT5
nPCIEXC5
PIN ASSIGNMENT
VEE
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
VCC
nOE0
nOE1
VCC
PCIEXC3
PCIEXT3
PCIEXC4
PCIEXT4
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 PCIEXC0
26 PCIEXT0
25 FS0
24 nCLK
23 CLK
22 PLL_BW
2 1 VCCA
20 VEE
19 BYPASS
18 FS1
17 PCIEXT5
16 PCIEXC5
15 VCC
ICS9DB306
28-LeadTSSOP, 173-MIL
4.4mm x 9.7mm x 0.92mm
body package
L Package
Top View
ICS9DB306
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm
body package
F Package
Top View
9DB306BL
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REV. A APRIL 7, 2005
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1k
TYPICAL PHASE NOISE AT 100MHZ
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
PCI Express™ Filter
100MHz
RMS Phase Jitter (Random)
1.5MHz to 22MHz = 3ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
PCI Express™ Filter to raw data
10k
100k
1M
10M 100M
OFFSET FREQUENCY (HZ)
The illustrated phase noise plot was taken using a low phase
noise signal generator, the noise floor of the signal generator is
less than that of the device under test.
Using this configuration allows one to see the true spectral pu-
rity or phase noise performance of the PLL in the device under
test. Due to the tracking ability of a PLL, it will track the input
signal up to its loop bandwidth.Therefore, if the input phase noise
is greater than that of the VCO, it will increase the output phase
noise performance of the device. It is recommended that the
phase noise performance of the input is verified in order to
achieve the above phase noise performance.
9DB306BL
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POWER CONSIDERATIONS
ICS9DB306
PCI EXPRESS,
JITTER ATTENUATOR
This section provides information on power dissipation and junction temperature for the ICS9DB306.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS9DB306 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW
• Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30mW = 180mW
Total Power (3.465V, with all outputs switching) = 467.8mW + 180mW = 647.8mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.9°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.648W * 43.9°C/W = 98.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 28-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
82.9°C/W
49.8°C/W
200
68.7°C/W
43.9°C/W
500
60.5°C/W
41.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
9DB306BL
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