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PDF ICS9DB102 Data sheet ( Hoja de datos )

Número de pieza ICS9DB102
Descripción 2 Output PCI Express Buffer
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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No Preview Available ! ICS9DB102 Hoja de datos, Descripción, Manual

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Integrated
Circuit
Systems, Inc.
ICS9DB102
2 Output PCI Express* Buffer with CLKREQ# Function
Recommended Application:
• 1-to-2 Zero-delay or fanout buffer for PCI Express
Output Features:
• 2 - 0.7V current mode differential output pairs (HSCL)
Key Specifications:
• Cycle-to-cycle jitter < 35ps
• Output-to-output skew < 25 ps
Features/Benefits:
• CLKREQ# pin for outputs 1 and 4/output enable for
Express Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
• Spread Spectrum Compatible/tracks spreading input
clock for low EMI
• SMBus Interface/unused outputs can be disabled
Pin Configuration
PLL_BW 1
CLK_INT 2
CLK_INC 3
**CLKREQ0# 4
VDD 5
GND 6
PCIEXT0 7
PCIEXC0 8
VDD 9
SMBDAT 10
20 VDDA
19 GNDA
18 IREF
17 **CLKREQ1#
16 VDD
15 GND
14 PCIEXT1
13 PCIEXC1
12 VDD
11 SMBCLK
Note: Pins preceeded by '**' have internal
120K ohm pull down resistors
20-pin SSOP & TSSOP
0852BC—09/12/05
DataSheet4 U .com
*Other names and brands may be claimed as the property of others.

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ICS9DB102 pdf
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9DB102
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, ΙREF = 475
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Zo
VHigh
VLow
Vovs
Vuds
VO = Vx
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
3000
660
-150
-300
850
150
1150
mV
mV
1
1,3
1,3
1,3
1,3
Crossing Voltage (abs) Vcross(abs)
250 350 550 mV 1,3
Crossing Voltage (var)
Long Accuracy
Average period
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Input to Output Delay
Duty Cycle
d-Vcross
ppm
Tperiod
Tabsmin
tr
tf
d-tr
d-tf
tpd
tpdbyp
dt3
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
PLL Mode.
Bypass mode
Measurement from differential
wavefrom
12 140 mV
0 ppm
9.9970
10.0030 ns
9.9970
10.0533 ns
9.8720
ns
175 700 ps
175 700 ps
30 125 ps
30 125 ps
135 185 ps
3.2 3.7 ns
45 55 %
1,3
1,2
2
2
1,2
1
1
1
1
1
1
1
Output-to-Output Skew
tsk3
VT = 50%
25 ps
Jitter, Cycle to cycle
tjcyc-cyc
PLL mode. Measurement from
differential wavefrom
35 ps
tjcyc-cycbyp
Additve Jitter in Bypass Mode
1Guaranteed by design, not 100% tested in production.
30
.
ps
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the
input clock complies with CK409/CK410 accuracy requirements
3IREF = VDD/(3xRR). For RR = 475(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
1
1
1
0852C—09/12/05
DataSheet4 U .com
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