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PDF SDA9290-5 Data sheet ( Hoja de datos )
| Número de pieza | SDA9290-5 | |
| Descripción | Picture Processor | |
| Fabricantes | Siemens Semiconductor | |
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Picture Processor
Preliminary Data
Features
q Noise and cross color reduction by field - or frame
recursive filtering
q 3 adjustments: 4-dB-, 7-dB- or 12-dB reduction
q Automatic adaption to signal quality during vertical
blanking
q Pixel adaptive movement detection
q Split screen modes for demonstration purposes
q Multi-picture facilities
q Picture decimation using vertical filtering
q 8 programmable grey levels for framing
q 4:1:1 and 4:2:2 (Y:U:V) compatibility
q 8-bit word size for all components
SDA 9290-5
NMOS IC
P-LCC-68-1
Type
SDA 9290-5
Ordering Code
Q67100-H5088
Package
P-LCC-68-1 (SMD)
Functional Description
The NMOS device SDA 9290-5 is a picture processor and belongs to a family of devices forming
an extended third-generation digital TV signal-processing system for enhanced picture quality with
special functions (Featurebox). Besides the Picture Processor (PP) that is described here, the
system consists of a field memory (at least three triple-port, 1-Mbit generation TV Sequential-
Access Memory devices (SDA 9251 X), a Memory Sync Controller (MSC SDA 9220-5) and a Video
D/A converter (SDA 9094-5). A block diagram of the Featurebox is shown in figure 1.
The Picture Processor SDA 9290-5 is a follow-on development of the Picture Processor SDA 9090
from the second-generation Featurebox and permits further picture improvement by reducing the
video noise and cross-color interference. The SDA 9290-5 can be set independently at the picture-
signal input and output via the two pins FSBQ/FSI to the 4:1:1 and 4:2:2 formats. A 4:1:1
Featurebox (3 TV-SAMs) can therefore be operated with 4:2:2 input signals as well.
Semiconductor Group
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SDA 9290-5
Register R0: This control register sets the operating mode of the picture processor.
Bits D7, D6:
Mode
Normal
Multi-picture (MP)
Still-in-picture (SIP)
Picture-in still (PIS)
B1 B0
00
01
10
11
*D
Bit D5:
MPP: Narrow Frame
Without narrow frame
With narrow frame
FR
0
1
Bit D4:
No function; default 0
Bit D3:
Display Mode
Full screen
Split screen
SS
0 *D
1
Specialities:
Split Screen Display
For demonstration purposes the noise reduction can be disabled for half of the picture by means of
I2C Bus register R0, bit D3. In this way a direct comparison is possible between a noise-reduced
(filtered) and an unfiltered picture.
Bit D2:
Bit D1:
Bit D0:
Control of SNR adaptation
TV mode
VCR mode
Noise reduction ON/OFF
Noise reduction OFF
Noise reduction ON
Word width input
7 bits
8 bits
VCR
0
1
*D
NR
0 *D
1
SUV8
0
1
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SDA 9290-5
Pin Definitions and Functions (cont’d)
Pin
No.
50
51
52
53
54
55
56
57-59
60
61-68
Symbol
SDA
VS1
VDD
FSBQ
FSI
CLKEN
SPEN
N.C.
VSS
YQ7 …
YQ0
Function
Description
I2C Bus data
input/output
I2C Bus data input/output
Vertical sync input Vertical sync input; determines vertical position of TV
(50 Hz)
picture for 50-Hz or 60-Hz field frequency
Positive supply
voltage (+ 5 V)
Positive supply voltage (+ 5 V)
Selection of output Switching of data output format:
format
Low level for 4:1:1 format; high level for 4:2:2 format
Selection of input Switching of data input format: Low level for 4:1:1 format;
format
high level for 4:2:2 format
Connect test pin 2 Has to be grounded (0 V) in normal mode
Connect test pin 2 Has to be grounded (0 V) in normal mode
Reserved
No connections possible or meaningful
Ground
Ground (0 V)
Data outputs
Push-pull outputs for directly driving TV-SAM inputs for
4:1:1 and 4:2:2 modes; (8-bit luminance)
Absolute Maximum Ratings
(all voltages are referred to VSS)
Parameter
Ambient temperature
Storage temperature
Total power dissipation
Supply voltage
Input/output voltage
Thermal resistance system-air
Operating Range
Supply voltage
Supply current
Ambient temperature
Symbol
TA
Tstg
Ptot
VDD
VI/Q
Rth SA
Limit Values Unit Remarks
min. max.
0 70 °C
– 40 125
°C
2.5 W
– 0.3 6
V
– 0.3 6
V
25 K/W with heat sink
VDD 4.5 5.5 V
IDD 450 mA
TA 0 70 °C
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