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PDF S1D13506 Data sheet ( Hoja de datos )
| Número de pieza | S1D13506 | |
| Descripción | Color LCD/CRT/TV Controller | |
| Fabricantes | Epson Company | |
| Logotipo |  |
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S1D13506 Color LCD/CRT/TV Controller
S1D13506
TECHNICAL MANUAL
Document Number: X25B-Q-001-06
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
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ENERGY
S AV I N G
EPSON
GRAPHICS
S1D13506
S1D13506 COLOR LCD/CRT/TV CONTROLLER
March 2001
The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of CPUs and display devices.
The S1D13506 architecture is designed to meet the low cost, low power requirements of the embedded
markets, such as Mobile Communications, Hand-Held PC’s, and Office Automation.
The S1D13506 supports multiple CPUs, all LCD panel types, CRT, TV, and additionally provides a number of
differentiating features. Products requiring digital camera input can take advantage of the directly supported
WINNOV VideumCam™ digital interface. EPSON Independent Simultaneous Display allows the user to configure
two different images on two different displays, while the SwivelView™, Hardware Cursor, Ink Layer, and BitBLT
engine offer substantial performance benefits. These features, combined with the S1D13506’s Operating System
independence, make it an ideal display solution for a wide variety of applications.
s FEATURES
• 16-bit EDO-DRAM or FPM-DRAM interface.
• Memory size options:
512K bytes using one 256K×16 device.
2M bytes using one 1M×16 device.
• Multiple CPU interface support.
• Resolutions up to:
640x480 at a color depth of 16 bpp.
800x600 at a color depth of 16 bpp.
• Display Support for:
4/8/16-bit passive panels.
9/12 TFT/D-TFD panels.
18-bit TFT/D-TFD to a depth of 64K colors.
CRT.
NTSC and PAL TV Output.
• SwivelView™: 90°, 180°, 270° hardware
rotation of displayed image.
• EPSON Independent Simultaneous Display:
displays different images on different displays.
• Virtual Display Support: displays images larger
than the panel size through the use of panning.
• Hardware Cursor or full screen Ink Layer.
• 2D BitBLT Engine.
• WINNOV Videum® Cam digital camera interface.
• Software initiated Power Save Mode.
• Operating System Independent.
s SYSTEM BLOCK DIAGRAM
CPU
EDO-DRAM
FPM-DRAM
TV
OR
Control
Clock
Analog Out
S1D13506
Digital Out
CRT
AND
MediaPlug
Interface
Flat Panel
X25B-C-001-05
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Epson Research and Development
Vancouver Design Center
Page 5
8.3.2 General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8.3.3 MD Configuration Readback Registers . . . . . . . . . . . . . . . . . . . . . . . .128
8.3.4 Clock Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
8.3.5 Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8.3.6 Panel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
8.3.7 LCD Display Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
8.3.8 CRT/TV Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .145
8.3.9 CRT/TV Display Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .150
8.3.10 LCD Ink/Cursor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
8.3.11 CRT/TV Ink/Cursor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
8.3.12 BitBlt Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
8.3.13 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
8.3.14 Power Save Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . .170
8.3.15 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
8.3.16 Common Display Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . .172
8.3.17 MediaPlug Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .173
8.3.18 BitBlt Data Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .177
9 2D BitBlt Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9.2 BitBlt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10 Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
10.1 Image Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
10.2 Ink Layer/Hardware Cursor Buffers . . . . . . . . . . . . . . . . . . . . . . 182
10.3 Dual Panel Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
11 Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
11.1 Display Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . 183
11.2 Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
13 TV Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
13.1 NTSC/PAL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
13.2 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
13.3 Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
13.3.1 Chrominance Filter (REG[05Bh] bit 5) . . . . . . . . . . . . . . . . . . . . . . . .189
13.3.2 Luminance Filter (REG[05Bh] bit 4) . . . . . . . . . . . . . . . . . . . . . . . . .189
13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1]) . . . . . . . . . . . . . . . . . . . . . . 189
13.4 TV Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.5 TV Image Display and Positioning . . . . . . . . . . . . . . . . . . . . . . 193
Hardware Functional Specification
Issue Date: 01/02/06
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S1D13506
X25B-A-001-10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S1D13506.PDF ] | |
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